AM69 datasheet(250/312 Pages) TI

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6.10.5.17.1.3 High Speed DDR Mode

Table 6-63, Figure 6-81, Table 6-64, and Figure 6-82 present timing requirements and switching characteristics

for MMC0 – High Speed DDR Mode.

Table 6-63. MMC0 Timing Requirements – High Speed DDR Mode

see Figure 6-81

NO.

MIN

MAX

UNIT

HSDDR1

tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

3.79

HSDDR2

th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

2.67

HSDDR3

tsu(dV-clkV)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition

0.74

HSDDR4

th(clkV-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition

1.67

Figure 6-81. MMC0 – High Speed DDR Mode – Receive Mode

Table 6-64. MMC0 Switching Characteristics – High Speed DDR Mode

see Figure 6-82

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

HSDDR5

tc(clk)

Cycle time, MMC0_CLK

HSDDR6

tw(clkH)

Pulse duration, MMC0_CLK high

9.2

HSDDR7

tw(clkL)

Pulse duration, MMC0_CLK low

9.2

HSDDR8

td(clkH-cmdV)

Delay time, MMC0_CLK rising edge to MMC0_CMD transition

3.4

9.8

HSDDR9

td(clkV-dV)

Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition

2.9

6.85

Figure 6-82. MMC0 – High Speed DDR Mode – Transmit Mode

AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

www.ti.com

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