440EPX datasheet(78/94 Pages) AMCC

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440EPx – PPC440EPx Embedded Processor

Preliminary Data Sheet

AMCC Proprietary

Revision 1.26 – October 15, 2007

TmrClk frequency

–

100

MHz

TmrClk period

–

TmrClk high time

40% of nominal period

60% of nominal period

TmrClk low time

40% of nominal period

60% of nominal period

Notes:

1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock

frequency is 83 MHz.

2. An internal PLL improves this duty cycle to a worst case of 48% minimum, 52% maximum.

3. Crystals, external clocks, or external oscillators must have a maximum tolerance of ±100ppm and maximum jitter of ±100ps.Only a

frequencies of 48MHz is allowed for oscillators; only a frequencies of 48MHz is allowed for crystals. Crystals and oscillators should be

connected as shown below:

PPC440EPx

Crystal

USB2XtalIn

PPC440EPx

Osc

USB2XtalOUT

USB2XtalOut

USB2XtalIn

C = 2(CL − CStray) where

Crystal – Frequency: 48MHz

Resonance mode: parallel

CO: 15–30pF

ESR: 20-60

CL is the load capacitance required by the crystal for oscillation

CStray is the board parasitic capacitance

Drive level: 50–500

μW

Table 19. Peripheral Interface Clock Timings (Sheet 3 of 3)

Parameter

Min

Max

Units

Notes

440EPX Datasheet(PDF) 78 Page - Applied Micro Circuits Corporation

440EPX Datasheet(HTML) 78 Page - Applied Micro Circuits Corporation

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