440EPX datasheet(91/94 Pages) AMCC

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440EPx – PPC440EPx Embedded Processor

Revision 1.26 – October 15, 2007

AMCC Proprietary

Preliminary Data Sheet

Initialization

The PPC440EPx provides the option for setting initial parameters based on default values or by reading them from

a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered

by strapping on external pins (see “Strapping” below).

Strapping

While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default

initial conditions prior to PPC440EPx start-up. The actual capture instant is the nearest reference clock edge

before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down

(logical 0) resistors to select the desired default conditions. These pins are used for strap functions only during

reset. Following reset they are used for normal functions. The signal names assigned to the pins for normal

operation are shown in parentheses following the pin number.

Note: When UART0_DCD, UART0_DSR and UART0_CTS are used functionally, the pin straps should be isolated

from the UART transceiver during reset as the transceiver may overdrive the pin straps and cause the PPC440EPx

to read incorrect straps.

The following table lists the strapping pins along with their functions and strapping options:

Function

Option

Pin Strapping

C28

(UART0_DCD)

C29

(UART0_DSR)

A29

(UART0_CTS)

Serial device is disabled. Each of the six options (A–

F) is a combination of boot source, boot-source

width, and clock frequency specifications. Refer to

the IIC Bootstrap Controller chapter in the

PPC440EPx Embedded Processor User’s Manual

for details.

Serial device is enabled. The option being selected is

the IIC0 slave address that will respond with

strapping data.

G (0xA8)

H (0xA4)

Serial EEPROM

During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device

connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440EPx

sequentially reads 16B from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,

SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly.

The initialization settings and their default values are covered in detail in the PowerPC 440EPx User’s Manual.

Table 27. Strapping Pin Assignments

440EPX Datasheet(PDF) 91 Page - Applied Micro Circuits Corporation

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