440EPX datasheet(89/94 Pages) AMCC

89 / 94 page

Notes:

1. Clock speed is 166MHz. TSK is referenced to MemClkOut falling edge. TSA and THA are referenced to MemClkOut rising

edge.

2. The timing in this table assumes a single registered DIMM load on the outputs. To adjust the timing for unbuffered DIMMs,

use the following values by subtracting them from TSA and adding them to TSK and THA:

5 loads adjust by 0.41ns

9 loads adjust by 1.12ns

18 loads adjust by 2.12ns

3. To obtain adjusted TSA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and subtract

TSK maximum (0.5TCYC − TSKmax).

4. To obtain adjusted THA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and add

TSK minimum (0.5TCYC + TSKmin).

Signal Name

TSK (ns)

TSA (ns)

THA (ns)

Minimum

Maximum

Minimum

MemAddr00:13

-0.960

-0.270

3.27

2.04

BA0:2

BankSel0:1

ClkEn

CAS

RAS

440EPx – PPC440EPx Embedded Processor

Revision 1.26 – October 15, 2007

AMCC Proprietary

Preliminary Data Sheet

Notes:

1. TSD and THD are measured under worst case conditions.

2. Clock speed for the values in the table is 166 MHz.

3. The time values in the table include 1/4 of a cycle at 166MHz (6ns x 0.25 = 1.5 ns).

4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4

of the cycle time for the lower clock frequency (for example, TSD − 1.5 + 0.25TCYC).

Signal Names

Reference Signal

TSD (ns)

THD (ns)

MemData00:07, DM0

DQS0

1.37

1.23

MemData08:15, DM1

DQS1

1.41

1.18

MemData16:23, DM2

DQS2

1.40

1.17

MemData24:31, DM3

DQS3

1.41

1.20

MemData32:39, DM4

DQS4

1.45

1.18

MemData40:47, DM5

DQS5

1.40

1.18

MemData48:55, DM6

DQS6

1.46

1.17

MemData56:63, DM7

DQS7

1.45

1.10

ECC0:7, DM8

DQS8

1.46

1.18

DDR SDRAM Read Operation

The read data capture logic is responsible for capturing the data outputs from the SDRAM devices and passing the

data back to the system clock domain. The data strobe signal (DQS) signals used to capture data are delayed to

ensure that the rising and falling edges of these strobes are in the middle of the valid window of data.

DDR devices send a DQS coincident with the read data so that the data can be reliably captured by the

PPC440EPx. The edges of these strobe signals are aligned with the data output by the SDRAM devices.

In order to reliably latch the data into a synchronizing FIFO, the PPC440EPx produces an internal, delayed version

of DQS. The amount of delay is user programmable. In the example shown in Figure 12, the delay is set to

approximately 25% of the system clock. A delay compensation circuit in the PPC440EPx keeps this delay

Table 25. I/O Timing—DDR SDRAM TSK, TSA, and THA

Table 26. I/O Timing—DDR SDRAM TSD and THD

440EPX Datasheet(PDF) 89 Page - Applied Micro Circuits Corporation

440EPX Datasheet(HTML) 89 Page - Applied Micro Circuits Corporation

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