440EPX datasheet(87/94 Pages) AMCC

87 / 94 page

Signal Path

Output Current (mA)

I/O H (maximum)

I/O L (maximum)

Write Data

MemData00:63

ECC0:7

DM0:8

MemClkOut

MemAddr00:13

BA0:2

RAS

CAS

BankSel0:1

ClkEn

DQS0:8

MemODT0:1

440EPx – PPC440EPx Embedded Processor

Revision 1.26 – October 15, 2007

AMCC Proprietary

Preliminary Data Sheet

DDR SDRAM Write Operation

The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is

generated by means of simulation and includes logic, driver, package RLC, and lengths. Values are calculated

over best case and worst case processes with speed, junction temperature, and voltage as follows:

Case

Process Speed

Junction Temperature (°C)

Voltage (V)

Best

Fast

−40

+1.6

Worst

Slow

+125

+1.425

Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and

maximum values are measured under worst case conditions. The timing numbers in the following sections are

obtained using a simulation that assumes a model as shown in Figure 10.

The following diagram illustrates the relationship among the signals involved with a DDR write operation.

Table 22. DDR SDRAM Output Driver Specifications

Table 23. DDR SDRAM Write Operation Conditions

440EPX Datasheet(PDF) 87 Page - Applied Micro Circuits Corporation

440EPX Datasheet(HTML) 87 Page - Applied Micro Circuits Corporation

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