TMPR4956C datasheet(183/286 Pages) TOSHIBA

183 / 286 page

Chapter 11 TX4956 System Interface

11-15

11.2.8.4 Processor single write requests

There are three processor single write requests as follow below.

With later G2SConfig register, these modes are selected.

R4000 compatible write

Reissue write

Pipeline write

Table 11.2.4 Data Transfer Rate, Data Pattern and Setting at single write requests

Maximum Data Transfer Rate

(64-bit width bus mode)

Data Pattern Setting Bits 2-1

Write mode

1 double word/3 MasterClock cycle

Dxx

R4000 compatible

Reserved

1 double word/1 MasterClock cycles

Pipeline write

1 double word/1 MasterClock cycles

Reissue write

Maximum Data Transfer Rate

(32-bit width bus mode)

Data Pattern Setting Bits 2-1

Write mode

1 word/3 MasterClock cycle

Wxx

R4000 compatible

Reserved

1 word/1 MasterClock cycles

Pipeline write

1 word/1 MasterClock cycles

Reissue write

Note:

The setting bits 2-1 is bits 2-1 of the G2Sconfig register (0xF FF10 0000).

Bits 2-1 is set to “00” when initialized.

R4000 compatible write

When in the R4000 compatible write mode, 4 cycles are required for single write operation.

After the address is asserted for 1 cycle, it is followed by 2 cycles of dummy data. Figure

11.2.14 illustrates its basic operation.

In the case of the TX4956, the WrRdy* signal must be asserted for 1 cycle 2 cycles before the

write operation is issued. When in the R4000 compatible signal write mode, the external agent

receives the write data then immediately asserts WrRdy*, making it possible to stop write

operation that continues after 4 cycles. The 2 cycles of dummy data that follow these write data

give the external agent time to stop the next write operation.

TMPR4956C Datasheet(PDF) 183 Page - Toshiba Semiconductor

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