TMPR4956C datasheet(187/286 Pages) TOSHIBA

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Chapter 11 TX4956 System Interface

11-19

The processor continues processing external requests while ExtRqst* is asserted. However, until

the processor completes a request that is currently being processed, it will not be able to release the

system interface and put it into the slave state in preparation for the next external request. Also, until

ExtRqst* is asserted, a series of external requests cannot be interrupted by a processor request.

11.2.8.7 External arbitration protocol

As previously mentioned, the ExtRqst* signal and Release* signal are used in system interface

arbitration. Figure 11.2.18 illustrates the timing of the arbitration protocol when the slave state

changes to the master state.

The arbitration cycle sequence is as follows.

The external agent asserts ExtRqst* when it becomes necessary to issue external requests.

The processor asserts Release* for 1 cycle when it becomes possible to process an external

request.

The processor sets the SysAD bus and SysCmd bus to tri-state.

The external agent must start transmission to the SysAD bus and SysCmd bus 2 cycles after

Release* is asserted.

The external agent deasserts ExtRqst* 2 cycles after Release* is asserted. This does not apply

however to situations where an attempt is made to issue another external request.

The external agent sets the SysAD bus and SysCmd bus to tri-state when processing of the

external request is complete.

The processor becomes able to issue processor requests 1 cycle after the external agent sets the

busses to tri-state.

Note:

The timing of the SysADC bus and SysCmdP bus are the same as the timing of the

SysAD bus and SysCmd bus timing, respectively.

Figure 11.2.18 Arbitration Protocol Relating to External Requests

Master

Slave

Master

Cycle

MasterClock

SysAD Bus

ValidIn*

WxtRqst*

SysCmd Bus

Cmd

Release*

NEOD

Addr

Data0

TMPR4956C Datasheet(PDF) 187 Page - Toshiba Semiconductor