TMPR4956C datasheet(190/286 Pages) TOSHIBA

190 / 286 page

Chapter 11 TX4956 System Interface

11-22

11.2.8.10 External write request protocol

The same protocol as the processor single word write protocol is used for external write requests,

except when the ValidIn* signal is asserted instead of the ValidOut* signal.

Figure 11.2.21 illustrates the timing of the external write request, which consists of the following

steps.

The external agent requests use of the system interface by asserting ExtRqst*.

The processor asserts Release*, then the system interface is released from the processor and

goes into the slave state.

The external agent sends a write command to the SysCmd bus, and sends a write address to the

SysAD bus while asserting ValidIn*.

The external agent sends data identifiers to the SysCmd bus, and sends data to the SysAD bus

while asserting ValidIn*.

Data identifiers for this data cycle must contain an indication of a coherent or non-coherent

final data cycle.

After a data cycle is issued, the write request is complete, the external agent sets the SysCmd

and SysAD busses to tri-state, then the system interface returns to the master state.

Note:

The timing of the SysADC bus and SysCmdP bus are the same as the timing of the

SysAD bus and SysCmd bus timing, respectively.

External write requests can write only 1 word of data to the processor. Operation of processors

that have specified data elements other than a single word of data by an external write request is not

defined.

Figure 11.2.21 External Write Request when System Interface Starts in the Master State

Cycle

MasterClock

SysAD Bus

ValidOut*

Validln*

SysCmd Bus

ExtRqst*

Release*

Master

Addr

Data0

Slave

Master

Write

NEOD

TMPR4956C Datasheet(PDF) 190 Page - Toshiba Semiconductor