TMPR4956C datasheet(207/286 Pages) TOSHIBA

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Chapter 11 TX4956 System Interface

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11.3.3.2 Load Miss

When the processor misses in the data cache on a load, it obtains a cache line of data from an

external agent. The processor issues a read request for the cache line and waits for an external agent

to provide the data in response to this read request. If the cache data which the incoming line will

replace contains valid dirty data, this data is written to memory. The read request completes before

the write of the dirty cast-out data because TX4956 has the write buffer.

11.3.3.3 Store Miss

When the processor misses in the data cache on a store, it issues a read request to bring a cache line

of data into the cache, where it is then updated with the store data. If the cache data which the

incoming line will replace contains valid dirty data, the data is written to memory. The read request

completes before the write of the dirty cast-out data because TX4956 has the write buffer.

To guarantee that cached data written by a store is consistent with main memory, the

corresponding cache line must be explicitly flushed from the cache using a cache operation.

11.3.3.4 Uncached Load or Store

When the processor performs an uncached load, it issues a read request and waits for a single

transfer of read response data from an external agent.

When the processor performs an uncached store, it issues a write request and provides a single

transfer of data to the external agent.

The processor does not consolidate data on uncached writes. For example, writes of two

contiguous halfwords takes two write cycles, they are never grouped into a single word write.

11.3.3.5 Cache Instructions

The TX4956 processor provides a number of cache instructions for use in maintaining the state

and contents of the caches. Cache operations supported in the TX4956 processor are described in

Chapter 5.

11.3.3.6 Byte Ordering (Endian)

The System interface byte order is set by the Endian of external pin. The byte order is big-endian

when Endian is high, and little-endian when Endian is low. The RE (reverse-endian) bit in the Status

11.3.3.7 Physical Addresses

Physical addresses are driven on SysAD[31:0] during address cycles.

TMPR4956C Datasheet(PDF) 207 Page - Toshiba Semiconductor