TMPR4956C datasheet(208/286 Pages) TOSHIBA

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Chapter 11 TX4956 System Interface

11-40

11.3.3.8 Interface Buses

Figure 11.3.1 shows the primary communication paths for the System interface: a 32-bit address

and data bus, SysAD[31:0], and a 5-bit command bus, SysCmd[4:0]. These SysAD and the SysCmd

buses are bidirectional; that is, they are driven by the processor to issue a processor request, and by

the external agent to issue an external request.

A request through the System interface consists of:

•

an address

•

a System interface command

•

a series of data elements if the request is for a write or read response.

Figure 11.3.1 System Interface Buses

11.3.3.9 Address and Data Cycles

The SysCmd bus identifies the contents of the SysAD bus during any cycle in which it is valid.

Cycles in which the SysAD bus contains a valid address are called address cycles. Cycles in which

the SysAD bus contains valid data are called data cycles. The most significant bit of the SysCmd bus

is always used to indicate whether the current cycle is an address cycle or a data cycle.

When the TX4956 processor is driving the SysAD and SysCmd buses, the System interface is in

master state. When the external agent is driving the SysAD and SysCmd buses, the System interface

is in slave state.

•

When the processor is master, it asserts the PValid* signal when the SysAD and SysCmd

buses are valid.

•

When the processor is slave, an external agent asserts the EValid* signal when the SysAD

and SysCmd buses are valid.

The SysCmd bus identifies the contents of the SysAD bus during valid cycles.

•

During address cycles (SysCmd[4] = 0), the remainder of the SysCmd bus, SysCmd[3:0],

contains a System interface command, described in Section 11.3.18 in detail.

•

During data cycles (SysCmd[4] = 1), the remainder of the SysCmd bus, SysCmd[3:0],

contains a data identifier, described in Section 11.3.18 in detail.

TX4956

SysCmd[4:0]

SysAD[31:0]

External Agent

TMPR4956C Datasheet(PDF) 208 Page - Toshiba Semiconductor