TMP88CS38FG datasheet(37/226 Pages) TOSHIBA

37 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-37

1.7.2

Control

The ROM corrective function is controlled by ROM corrective control register (ROMCCR)

and ROM corrective data register (ROMCDR).

ROM Corrective Control Register

ROMCCR

(00FE0H)

−

CM3

CM2

CM1

CM0

(Initial value: **** 0000)

CM3

Corrective mode setting

(BANK3)

CM2

Corrective mode setting

(BANK2)

CM1

Corrective mode setting

(BANK1)

CM0

Corrective mode setting

(BANK0)

0: Proguram jump mode

1: Data replacement mode

R/W

ROM Corrective Status Register

ROMCSR

(00FE1H)

−

WDC

(Initial value: ***0 0000)

WDC

Write data counter

Counting the number of the byte written in ROMCDR

Read

only

ROM Corrective Data Register

ROMCDR

(00FE2H)

(Initial value: 0000 0000)

ROMC

ROM Corrective data register

Write

only

Figure 1.7.2 ROM Corrective Control Register, Status Register and ROM Corrective Data Register

(1) Enable and disable

The ROM corrective function is disabled after releasing reset. It is enabled after

setting the data for one bank into ROMCDR. And the address-trap-reset is not

generated when fetching an instruction from the RAM area except the address 02C0H

to 08BFH.

After the ROM corrective function is enabled, it is necessary to reset the

microcontroller in order to disable it.

(2) Data replacement mode

The ROM corrective function has the program jump mode and the data replacement

mode.

By setting CMx (x: 0 to 3) in ROMCCR, the data replacement mode is selected.

(3) The ROM corrective data register writing

The ROM corrective data register has four banks corresponding to four independent

locations to patch. The write data counter (WDC) points each bank set. (Figure 1.7.2)

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