TMP88CS38FG datasheet(57/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-57

2.4.2

Watchdog Timer Control

Figure 2.4.2 shows the watchdog timer control registers (WDTCR1, WDTCR2). The

watchdog timer is automatically enabled after reset.

(1) Malfunction detection methods using the watchdog timer

The CPU malfunction is detected at follows.

1. Setting the detection time, selecting output, and clearing the binary counter.

2. Repeatedly clearing the binary counter within the setting detection time.

Note:

The watchdog timer consists of an internal divider and two-stage binary counter.

Writing the clear code (4EH) clears the binary counter, but not the internal divider.

The minimum overflow time for the binary counter might be three quarters of the

WDTCR1 (WDTT) time setting depending on when the clear code (4EH) is written

into the WDTCR2 register. So, write the clear code on a cycle which is shorter than

that minimum overflow time.

If the CPU malfunctions such as endless looping or deadlock occur for any cause, the

watchdog timer output will become active at the rising of an overflow from the binary

counters unless the binary counters are cleared. At this time, when WDTOUT

= 1 a

reset is generated, which drivers the RESET pin low to reset the internal hardware

and the external circuit. When WDTOUT

= 0, a watchdog timer interrupt (INTWDT) is

generated.

The watchdog timer temporarily stops counting in STOP mode including warm-up or

IDLE mode, and automatically restarts (Continues counting) when the STOP/IDLE

mode is released.

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