TMP88CS38FG datasheet(70/226 Pages) TOSHIBA

70 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-70

2.6.2

Control

The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a

16-bit timer register 2 (TC2DR). Reset does not affect TC2DR.

TC2DR

(00016H, 00017H)

TC2DRH (00017H)

TC2DRL (00016H)

Read/Write

TC2CR

(00015H)

TC2S

TC2CK

TC2M

(Initial value: **00 00*0)

TC2M

TC2

operating mode select

0: Timer/event counter mode

1: Window mode

NORMAL1/2, IDLE1/2 mode

DV1CK

= 0

DV1CK

= 1

000

fc/2

001

fc/2

010

fc/2

011

fc/2

100

Reserved

101

Reserved

110

Reserved

TC2CK

TC2

source clock select [Hz]

111

External clock (TC2 pin input)

TC2S

TC2

start control

0: Stop and counter clear

1: Start

Write

only

Note 1:

fc: High-frequency clock [Hz], *: Don’t care.

Note 2:

Writing to the lower byte of timer register 2 (TC2DRL), the comparison is inhibited until the upper byte (TC2DRH) is

written. After writing to the upper byte, any match during 1 machine cycle (Instruction execution cycle) is ignored.

Note 3:

Set the mode and source clock when the TC2 stops (TC2S

= 0).

Note 4:

Values to be loaded to timer registers must satisfy the following condition.

TC2DR

> 1

Note 5:

TC2CR are write-only registers and must not be used with any of the read-modify-write instructions.

Note 6:

When STOP mode is started, timer counter is stopped and cleared. Set TC2S to “1” after STOP mode is released for

restarting timer counter.

Figure 2.6.2 Timer Registers 2 and TC2 Control Register

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