TMP88CS38FG datasheet(38/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-38

ROM Corrective Data Register

ROMCDR

(00FE2H) ROMC7 ROMC6 ROMC5 ROMC4 ROMC3 ROMC2 ROMC1 ROMC0

(Initial value: 0000 0000)

00000 (Initial value)

The lower start address of the corrective area (8 bits)

00001

The middle start address of the corrective area (8 bits)

00010

The upper start address of the corrective area (4 bits)

00011

The lower 8 bits of the jump address/replacement data

00100

The middle 8 bits of the jump address/replacement data

00101

The upper 4 bits of the jump address/replacement data

00110

The lower start address of the corrective area (8 bits)

00111

The middle start address of the corrective area (8 bits)

01000

The upper start address of the corrective area (4 bits)

01001

The lower 8 bits of the jump address/replacement data

01010

The middle 8 bits of the jump address/replacement data

01011

The upper 4 bits of the jump address/replacement data

01100

The lower start address of the corrective area (8 bits)

01101

The middle start address of the corrective area (8 bits)

01110

The upper start address of the corrective area (4 bits)

01111

The lower 8 bits of the jump address/replacement data

10000

The middle 8 bits of the jump address/replacement data

10001

The upper 4 bits of the jump address/replacement data

10010

The lower start address of the corrective area (8 bits)

10011

The middle start address of the corrective area (8 bits)

10100

The upper start address of the corrective area (4 bits)

10101

The lower 8 bits of the jump address/replacement data

10110

The middle 8 bits of the jump address/replacement data

10111

The upper 4 bits of the jump address/replacement data

00000

Note 1:

WDC value equals to the number of the byte stored in ROMCDR.

Note 2:

ROMCDR is set in order of the lower (8 bits), the middle (8 bits) and the upper (4 bits) start address of the

corrective area, the lower (8 bits), the middle (8 bits) and the upper (4 bits) of the jump address/the

replacement data.

Figure 1.7.3 Banks and WDC Value of the Program Corrective Data Register

Whenever ROMCDR is written, WDC is incremented to indicate what data is writen via

ROMCDR. During reset, WDC is initialized to “0”.

(1) The lower start address of the corrective area (8 bits)

(2) The middle start address of the corrective area (8 bits)

(3) The upper start address of the corrective area (4 bits)

(4) The lower jump address/replacement data (8 bits)

(5) The middle jump address/replacement data (8 bits)

(6) The upper jump address (4 bits)/replacement data

Note 1: Corrective addresses must have over five addresses each other.

Note 2: The address of a instruction for IDLE mode can not be specificated as start address of

corrective area.

BANK0

BANK1

BANK2

BANK3

The value of WDC after writing a data to ROMCDR

TMP88CS38FG Datasheet(PDF) 38 Page - Toshiba Semiconductor

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