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TMP88CS38FG Datasheet(PDF) 14 Page - Toshiba Semiconductor

Part # TMP88CS38FG
Description  8-bit single chip microcomputer
PDF  226 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP88CS38FG Datasheet(HTML) 14 Page - Toshiba Semiconductor

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TMP88CS38/CM38A/CP38A
2007-09-12
88CS38-14
1.4.4
Operating Mode Control
(1) STOP mode
STOP mode is controlled by the system control register 1 (SYSCR1) and the STOP
pin input. The STOP pin is also used both as a port P20 and an INT5 (External
interrupt input 5) pin. STOP mode is started by setting STOP (Bit7 in SYSCR1 ) to “1”.
During STOP mode, the following status is maintained.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers and port output latches are all held in the status in
effect before STOP mode was entered.
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address of the instruction following the instruction
which started the STOP mode.
STOP mode includes a level-sensitive release mode and an edge-sensitive release
mode, either of which can be selected with RELM (Bit6 in SYSCR1).
a. Level-sensitive release mode (RELM
= 1)
In this mode, STOP mode is released by setting the STOP pin high. This mode
is used for capacitor backup when the main power supply is cut off and long term
battery backup.
When the STOP pin input is high, executing an instruction which starts the
STOP mode will not place in STOP mode but instead will immediately start the
release sequence (Warm up). Thus, to start STOP mode in the level-sensitive
release mode, it is necessary for the program to first confirm that the STOP pin
input is low. The following method can be used for confirmation:
Using an external interrupt input INT5 ( INT5 is a falling edge-sensitive input).
Example: Starting STOP mode with an INT5 interrupt.
PINT5:
TEST
(P2). 0
;
JRS
F, SINT5
To reject noise, the STOP mode does not start if port
P20 is at high
LD
(SYSCR1), 01010000B
;
Sets up the level-sensitive release mode
SET
(SYSCR1). 7
;
Starts STOP mode
LDW
(IL), 1110011101010111B
;
IL12, 11, 7, 5, 3 ← 0 (Clears interrupt latches)
SINT5:
RETI
Note 1:
After warming up is started, when STOP pin input is changed “L” level, STOP mode is not placed.
Note 2:
When changing to the level-sensitive release mode from the edge-sensitive release mode, the release
mode is not switched until a rising edge of the STOP pin input is detected.
Figure 1.4.9 Level-sensitive Release Mode
STOP
pin
XOUT pin
NORMAL
operation
Confirm by program that the
STOP
pin input is low and
start STOP mode.
VIH
STOP mode is released by the hardware.
Always released if the STOP
pin input is high.
NORMAL
operation
STOP
operation
Warm up



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