| Electronic Components Datasheet Search |
|
TMP88CS38FG Datasheet(PDF) 64 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMP88CS38FG Datasheet(HTML) 64 Page - Toshiba Semiconductor |
|
64 / 226 page ![]() TMP88CS38/CM38A/CP38A 2007-09-12 88CS38-64 Figure 2.5.3 Timer Mode Timing Chart (2) External trigger timer mode In this mode, counting up is started by an external trigger. This trigger is the edge of the TC1 pin input. Either the rising or falling edge can be selected with TC1S. Source clock is an internal clock. The contents of TC1DRA is compared with the contents of up counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to “0” and halted. The counter is restarted by the selected edge of the TC1 pin input. When METT1 (Bit6 in TC1CR) is “1”, inputting the edge to the reverse direction of the trigger edge to start counting clears the counter, and the counter is stopped. Inputting a constant pulse width can generate interrupts. When METT1 is “0”, the reverse directive edge input is ignored. The TC1 pin input edge before a match detection is also ignored. The TC1 pin input has the noise rejection; therefore, pulses of 7/fc [s] or less are rejected as noise. A pulse width of 13/fc [s] or more is required for edge detection in NORMAL or IDLE mode. Example 1: Detects rising edge in TC1 pin input and generates an interrupt 100 μs later. (at fc = 16.0 MHz, DV1CK = 1) LDW (TC1DRA), 0064H ; 100 μs ÷ 24/fc = 64H DI SET (EIRL). 4 ; INTTC1 interrupt enable EI LD (TC1CR), 00001000B ; Selects the source clock and mode LD (TC1CR), 00101000B ; TC1 external trigger start, METT1 = 0 Example 2: Generates an interrupt, inputting “L” level pulse (Pulse width: 4 ms or more) to the TC1 pin. (at fc = 16.0 MHz, DV1CK = 1) LDW (TC1DRA), 00FAH ; 4 ms ÷ 28/fc = FAH DI SET (EIRL). 4 ; INTTC1 interrupt enable EI LD (TC1CR), 00000100B ; Selects the source clock and mode LD (TC1CR), 01110100B ; TC1 external trigger start, METT1 = 1 n m m − 1 m m − 2 Up counter TC1DRB ACAP1 Capture m + 1m + 2 (b) Auto capture TC1DRA INTTC1 interrupt n − 1n n + 1 Capture Count start 1 Source clock Up counter Source clock 2 3 4 1 2 3 4 0 ? n n − 1n 0 5 6 7 Match detect Counter clear (a) Timer mode ? m − 1 m + 1m + 2n − 1 n + 1 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |