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TMP88CS38FG Datasheet(PDF) 78 Page - Toshiba Semiconductor

Part # TMP88CS38FG
Description  8-bit single chip microcomputer
PDF  226 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP88CS38FG Datasheet(HTML) 78 Page - Toshiba Semiconductor

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TMP88CS38/CM38A/CP38A
2007-09-12
88CS38-78
Figure 2.7.4 Event Counter Mode Timing Chart
(3) Capture mode
In this mode, the pulse width, period and duty of the TC3 pin input are measured in
this mode, which can be used in decoding the remote control signals or distinguishing
AC 50/60 Hz, etc. The TC3 pin input can have its polarity changed between normal and
inverse by using the TC3ES Register.
a. If TC3ES
= “0” (Non-inverting input)
Once command operation has started, the counter free-runs on an internal
source clock.
When the falling edge of the TC3 pin input is detected, the counter value is
loaded into TC3DRB. When the rising edge is detected, the counter value is loaded
into TC3DRA, and the counter is cleared, generating an INTTC3 interrupt.
If the rising edge is detected right after command operation has started, no
capture to TC3DRB and an INTTC3 interrupt occurs only on capture to TC3DRA.
If a read instruction is executed for TC3DRB, the value that exists at the end of
the previous capture (immediately after a reset, “FF”) is read.
b. If TC3ES
= “1” (Inverse input)
Once command operation has started, the counter free-runs on an internal
clock.
When the rising edge of the TC3 pin input is detected, the counter value is
loaded into TC3DRB. When the falling edge is detected, the counter value is
loaded into TC3DRA, and the counter is cleared, generating an INTTC3 interrupt.
If the falling edge is detected right after command operation has started, the
counter value is not captured into TC3DRB and an INTTC3 interrupt occurs only
on capture to TC3DRA. If a read instruction is executed for TC3DRB, the value
that exists at end of the previous capture (immediately after a reset, “FF”) is read.
The minimum acceptable input pulse width is equal to the length of one source
clock period selected by TC3CR <TC3CK>.
Table 2.7.3 TC3INV-based Capture Input Edges
TC3ES
Capture into TC3DRB
Capture into TC3DRA
INTTC3 Interrupt
“0”
(Non-inverting input)
Falling edge
Rising edge
“1”
(Inverting input)
Rising edge
Falling edge
Note:
Capture of the TC3 pin input requires at least 1 cycle of the selected source clock.
1
2
3
1
2
3
n
Timer register
INTTC3 interrupt
TC3 pin input
Up counter
0
n
Match detect
Counter clear
Count start
0
n
− 1



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