TMP88CS38FG datasheet(44/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-44

2.2

I/O Ports

The TMP88CS38/CM38A/CP38A has 6 parallel input/output ports (33 pins) as follows:

Primary Function

Secondary Functions

Port P2

1-bit I/O port

External interrupt input, and STOP mode release signal input

Port P3

6-bit I/O port

External interrupt input, remote control signal input, data slicer analog

input, timer/counter input, serial bus interface input/output and data

slicer input

Port P4

8-bit I/O port

Pulse width modulation output

Port P5

8-bit I/O port

Pulse width modulation output external interrupt input, timer/counter

input, key-on wakeup input, serial bus interface input/output, analog

input and I output from OSD circuitry.

Port P6

8-bit I/O port

R, G, B and Y/BL output from OSD circuitry, R.G.B and Y/BL input,

analog input, test video signal output and key-on wakeup input

Port P7

2-bit I/O port

Horizontal synchronous pulse input and vertical synchronous pulse

input to OSD circuitry

Each output port contains a latch, which holds the output data. All input ports do not have

latches, so the external input data should either be held externally until read or reading should

be performed several times before processing. Figure 2.2.1 shows input/output timing examples.

External data is read from an I/O port in the S1 state of the read cycle during execution of the

read instruction. This timing can not be recognized from outside, so that transient input such as

chattering must be processed by the program. Output data changes in the S2 state of the write

cycle during execution of the instruction which writes to an I/O port.

Note: The positions of the read and write cycles may vary, dispending on the instruction.

Figure 2.2.1 Input/Output Timing (Example)

Fetch cycle

Read cycle

S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3

Ex.: LD

A, (x)

(a) Input timing

Instruction

execution

cycle

Input strobe

Data input

Fetch cycle

Write cycle

S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3

Ex.: LD

(x), A

Instruction

execution

cycle

Output latch

pulse

Data output

(b) Output timing

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