ACT43750 datasheet(6/43 Pages) QORVO

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Data Sheet Rev. F, February 10, 2025 | Subject to change without notice

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ACT43750

RF POL Drain-Switch Driver / Gate-bias Regulator

PIN DESCRIPTIONS

NAME

DESCRIPTION

V50

Input power to the DSW50 control section of the IC.

2, 28

PGND

Dedicated power ground for the DSW50 gate drive. Connect to AGND with a Kelvin connection.

AGND

Ground pin for the analog blocks. Connect to PGND with a Kelvin connection.

XINT

Interrupt output. Open drain. Connect it through a pull-up resistor to V5.

5V Bias regulator output. Requires a 2.2uF capacitor to AGND

SDA

I2C Data Pin for Slave mode

SCL

I2C Clock Pin for Slave mode

SCL50

I2C Data Pin for Master mode

SDA50

I2C Clock Pin for Master mode

ENTX

Enable input for the DSW50 block. Don't float this pin. Connect it through a 100k

Ω resistor to AGND.

ENTX pin needs to be logic low when startup.

ENCAL

Enable input to start an autocalibration routine. Don't float this pin. Connect it through a 100k

Ω resistor to

AGND.

SYNC

External clock synchronization input

CONF

External configuration resistor input. Connect a resistor between CONF and V5 and between CONF and

AGND to configure IC settings.

Sets the negative gate voltage switching frequency. Connect a resistor between RT and AGND.

REFIN

External voltage reference input. Leave open if not used.

NTC

Negative temperature coefficient resistor input.

ENG

Enable input for the REGG block (negative voltage regulator). Don't float this pin. Connect it through a

100k

Ω resistor to AGND.

Power good output. Open drain. Connect it through a pull-up resistor to V5.

GV5

Floating negative gate voltage output. Connect a 2.2uF capacitor between GV5 and VG.

GREF

The local voltage reference for the REGG output. Connect a 100nF capacitor between GREF and VG.

COMP

Compensation input. Connect a 470pF capacitor between COMP and VG.

Feedback input for the REGG output. Connect a 10nF capacitor between VG and V12.

GSW

REGG switching node.

V12

External 12V bias input pin. Connect a 10uF capacitor between V12 and PGND. Connect a 10nF capaci-

tor between V12 and VG.

LSR

Low-side gate drive regulator for the DSW50 block. Connect a 2.2uF capacitor between LSR and PGND.

LSGU

Pullup output for the low-side FET gate.

LSGD

Pulldown output for the low-side FET gate.

CPL

High-side gate drive regulator flying capacitor terminal. Connect a 47nF capacitor and a 33Ω resistor in

series between CPL and CPH.

CPH

High-side gate drive regulator flying capacitor terminal. Connect a 47nF capacitor and a 33

Ω resistor in

series between CPH and CPL.

CALG

Calibration FET gate output.

DSW50 output voltage for the high side FET. Connect a 10uF capacitor between VD and BT50.

BT50

High-side gate drive regulator bootstrap output. Connect a 10uF capacitor between BT50 and VD.

HSGD

Pulldown output for the high-side FET gate.

HSGU

Pullup output for the high-side FET gate.

CSPA

Overcurrent sense resistor input for the drain FET

CSCAL

Calibration current sense resistor input for the calibration FET.

Exposed PAD

Exposed thermal pad. Connect directly to PGND.

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