ACT43750 datasheet(20/43 Pages) QORVO

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Data Sheet Rev. F, February 10, 2025 | Subject to change without notice

20 of 43

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ACT43750

RF POL Drain-Switch Driver / Gate-bias Regulator

Figure 5 shows the ACT43750 detailed functional

blocks.

The ACT43750 provides the following three (3) major

functions.

REGG: generates the negative gate voltage

DSW50: generates the RF PA drain voltage

IDRAIN Calibrator: calibrates the RF PA’s gate

voltage to optimize the RF PA performance.

To support these 3 blocks, the device integrates the

following supporting function blocks.

•

Logic Interface

I2C Slave

I2C Master

I2C Bypass

•

Finite State Machine

•

Device Initialization / Configuration

External Configuration Resistors

Factory Programming Defaults

I2C Registers

•

Device Bias / Reference System

5-V Bias Regulator

Floating 5-V Bias Regulator

Low-side Gate Drive Regulator

High-side Gate Drive Regulator

Switching Clock Generator

DACG

•

Protection Circuitry

State Machine

The ACT43750 integrates a state machine to control the

overall IC behavior and operation. The following section

describes each state.

No Power

The IC starts up in this state and remains there until

the V12 input bias voltage goes above its UVLO,

typically 10V.

Bias Ramp

When the V12 bias voltage goes above ULVO, the state

machine moves to the Bias Ramp stage. In this state,

the IC initializes and loads the default CMI values from

NVM into working memory. It reads the voltage on

CONF and loads the resulting value into register 0x11h.

It reads bit 0x11h [6] and decides to use the internal

clock, which is set by the RRT resistor, or synchronize

with the external clock. It loads the REGG voltage ref-

erence to set the default negative gate voltage. After

these steps are complete and the bias voltages are

ready, the IC moves to the Bias Ready state.

Bias Ready

In the Bias Read state, the IC waits for an input trigger

to turn on the negative gate voltage, REGG.

REGG Ramp

When a REGG enable event is triggered, the device

starts up the REGG negative gate drive voltage.

REG50 Ramp

When the REGG voltage is ready, the VPG pin goes

open drain. This allows the IC to enable an external

drain voltage regulator if available. This state is in-

tended to enable the ACT43850 via I2C. It does this by

automatically using the Master I2C bus to write a 1 to

the ACT43850 register 0x08 bit[0].

TX Ready

When both the REGG and REG50 are ready, the IC en-

ters this state and waits for a command to enter one of

the following states: DSW50 ON, RSCAL CAL, REGG

to MIN, and REGG Programming.

DSW50 ON

In this state, the drain FET is turned on, and the drain

voltage is applied to the RF PA. Before the IC enters

this state, it must have entered either the RSCAL CAL,

REGG to MIN, or REGG Programming states.

RSCAL CAL

In this state, an autocalibration routine is performed to

find the proper gate voltage to bias the RF PA at the

desired drain current, Idq.

REGG to MIN

In this state, the REGG gate voltage slews to the mini-

mum programmed value to turn off the RF PA.

REGG Programming

The IC enters this state when an I2C command changes

the DACG register value. This value sets the REGG

negative gate voltage to the RF PA. The gate voltage

can only be changed when ENTX is low. That means

the IC can only enter this state when the drain voltage

is off.

Error REGG MIN

The IC enters this state when it detects an overcurrent

or over-temperature on the RF PA. The device turns off

the drain voltage and drives the REGG gate voltage to

the minimum programmed voltage.

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