Data Sheet Rev. F, February 10, 2025 | Subject to change without notice

14 of 43

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ACT43750

RF POL Drain-Switch Driver / Gate-bias Regulator

®

VD = V50 = 50V, V12 = 12V, VG = ‒2.5V, VBT50 = 55.2V, VSCL = VSDA = VENCAL = VENG = VENTX = VSCL50 = VSDA50 = VNTC = 5V, VREFIN =

0V, TA = ‒40 to +125 °C, unless otherwise specified

Note 1:Specified as a device internal logic delay, not an actual dead time at the VD pin

REGG Regulator System

fsw(MIN)

REGG Minimum Switching

Frequency

RRT = 215kΩ

-5%

1080

+5%

kHz

fsw(MAX)

REGG Maximum Switching

Frequency

RRT = 115kΩ

-10%

2050

+10%

kHz

fSPSP

REGG Spread-Spectrum

Dithering Range

+/-7

%

NSPSP

REGG Spread-Spectrum Cycle

64

cycle

tMIN(GSW)

GSW Output Pulse, MIN

50

ns

tMAX(GSW)

GSW Output Pulse, Max

50% x

(1/fSW)

tH(GREF)

GREF Holding Time

Operation change from IO(GREF) to RO(GREF)

5

ms

fC

Unity Gain Frequency/Loop

Bandwidth

10% fsw

Hz

PM

Phase Margin

45o

Gain

100 Hz Gain

60

dB