ACT43750 datasheet(36/43 Pages) QORVO

36 / 43 page

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice

36 of 43

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ACT43750

RF POL Drain-Switch Driver / Gate-bias Regulator

Rsf , Csf and CSPA

The Rsf resistor, CSf and CSPA capacitors form a RC filter

for the IDRAIN current sensing.

RSPA

TRHS

CSPA

Rsf

CSPA

V50

CSf

Figure 10. RC Filter for Drain Current Sense

Rsf

is 51Ω resistor, Csf and CSPA are 0.1µF ceramic ca-

pacitors.

Typical Startup Procedure

The typical startup procedure is outlined below.

The ENTX, ENCAL, and ENG digital input sig-

nals must be actively terminated low. The most

common system level startup errors occur

when these signals are not actively terminated

low.

The RT, NTC, and CONF resistors must be

populated with the correct values for the de-

sired operation.

Apply the V12 bias voltage and the V50 drain

voltage. These can be applied in any order.

Enable the gate voltage by driving the ENG pin

high. The user can also enable REGG via I2C

by writing a 1 into register 0x08h [7], the

EN_REGG bit. If using the Qorvo GUI, click the

Enable Vgate button. This enables the negative

gate voltage and programs it to the most nega-

tive value as defined by register 15.

Momentarily drive the ENCAL pin high to initi-

ate a calibration routine to bias the RF PA with

the correct gate voltage to achieve the desired

Idq current. ENCAL must be pulled low before

moving to the next step. The user can also en-

able calibration via I2C by writing a 1 into 0x08h

[3], the RunCal bit. If using the Qorvo GUI, click

the Autocalibration button. Note that excessive

RF PA drain capacitance can result in a large

inrush current that creates an overcurrent con-

dition when main power FET turns on to apply

the drain voltage to the RF PA. Refer to App

Note 5 in the

user’s guide for details and limita-

tions on the RF PA drain capacitance.

For systems with drain switching, drive the

ENTX pin high and low with the desired fre-

quency and duty cycle. For systems that oper-

ate with a continuous drain voltage, simply

drive ENTX high. If using the Qorvo GUI, click

the Enable Vdrain button.

If a calibration routine is needed at any time

during operation, pull ENTX low or disable the

drain voltage via I2C. Then enable the calibra-

tion routing by toggling the ENCAL pin high.

The user can also enable a recalibration routine

via I2C by writing a 1 into 0x08h [3], the RunCal

bit. If using the Qorvo GUI, click the Autocali-

bration button. Then enable the drain voltage

again with ENTX or via I2C.

Note that it’s possi-

ble to perform a recalibration in between trans-

mission pulses if the off-time is longer than the

calibration time.

Typical Turnoff Procedure

The typical turnoff procedure is outlined below.

Turn off the drain switch by pulling the ENTX

pin to a low logic level. For continuous opera-

tion, the drain switch can be disabled via I2C by

clicking Disable Vdrain in GUI.

Adjust the gate voltage to the minimum pro-

grammed voltage defined by register 15. This

puts the RF PA in pinchoff and turns off the

GaN FET.

Power off the drain power supply.

After the drain voltage decays to less than 10V,

turn off the 12V bias power supply

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