Data Sheet Rev. F, February 10, 2025 | Subject to change without notice

12 of 43

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ACT43750

RF POL Drain-Switch Driver / Gate-bias Regulator

®

Note 1, Operating below the minimum pulse width moves the IC to the Error Bias State. To return to normal operation, turn off the drain supply

voltage and bias voltage, then power up normally.

Parameter

Conditions

Min

Typ

Max

Units

Clock System

fSYNC

SYNC Clock Input Frequency

Range

Difference from the target set by RRT

-20

+20

%

DSYNC

SYNC Clock Input Pulse Duty

Cycle

40

60

%

I2C Slave for MCUs/Controllers

fSCL

SCL Clock Frequency

(no internal time out)

0

1000

kHZ

tLOW(SCL)

SCL Pulse Width, Low

0.5

µs

tHIGH(SCL)

SCL Pulse Width, High

0.26

µs

tSU(SDA)

SDA Set-up Time

50

ns

tH(SDA)

SDA Hold Time

0

ns

tFALL(SDA)

SDA Fall Time

SDA pull-up to 5V source via 10k

Ω

120

ns

tSU(START)

I2C START Set-up Time

260

ns

tSU(STOP)

I2C STOP Set-up Time

260

ns

I2C Master for ACT43850 and external I2C Memory

tFALL(SDA50)

SDA50 Fall Time

Slave devices (ACT43850 and external

I2C memory) driving SDA50

120

ns

Logic I/F

tL(Logic) (Note 1)

ENCAL, ENG, ENTX, PG

Pulse Width, Low

Minimum pulse width

40

µs

tH(ENTX) (Note 1)

ENTX Pulse Width, High

Minimum pulse width

12

µs