ACT43750 datasheet(32/43 Pages) QORVO

32 / 43 page

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice

32 of 43

www.qorvo.com

ACT43750

RF POL Drain-Switch Driver / Gate-bias Regulator

Internal Clock Generator

The ACT43750 contains an internal clock generator

block for the REGG switching converter. This oscillator

can operate stand-alone, or it can be synchronized to

or from an external clock. This allows the system to syn-

chronize the REGG switching frequency to an external

oscillator.

Internal Clock Oscillator

When bit 0x11h [6] = 0, the clock generator uses its in-

ternal oscillator. This oscillator generates its switching

frequency based on a resistor value connected to the

RT pin. The target switching frequency fSW follows

equation (3). Table 8 provides some example values.

��(MHz) =

221

��0.982(��Ω)

(3)

Table 8. Resistor value vs. Switching Frequency

RT Value (k

Ω)

Switching Frequency of REGG

(KHZ)

< 111

(error)

115

2043

125

1880

136

1728

150

1567

167

1407

188

1250

215

1093

> 231

(error)

When bit 0x11h [5] = 1, the IC shares this clock signal

with other regulator devices by sending it out from the

SYNC pin.

When 0x11h [5] bit = 0, the IC does not share the clock,

and operates in stand-alone operation.

Spread-spectrum.

When using the internal oscillator, this oscillator block

can enable/disable a spread-spectrum function. When

spectrum. When 0x10h [3] = 0, the device disables the

spread spectrum, and the output clock is fixed / steady.

The spread-spectrum function modulates, or dithers,

the internal clock frequency. The switching frequency

varies +/-

7% from the oscillator’s programmed fre-

quency, and repeats the dithering every 64 cycles.

External Clock Synchronization

When register 0x11h [6] = 1, the clock generator syn-

chronizes to an external clock input at the SYNC pin.

When 0x11h [4] = 0, the internal clock is synchronized

to the rising edge of the SYNC pin, and when it =

1, it’s

synchronized to the falling edge. When the SYNC pin is

configured as a slave input, the external frequency can

be divided down to switch at a slower frequency. The

fSYNC bits in 0x0Eh [7:5] can divide the SYNC frequency

down by a factor of 1 to 8.

Operation Frequency Selection / RRT

When using the Internal Clock Oscillator, equation 3

calculates the correct RT resistor value. This resistor

value is read by the IC at startup. It uses the value to

optimize internal settings such as compensation, pro-

tection settings, etc. The RT resistor must be used even

if the IC is configured as a slave. The RT value must be

chosen so that equation 3 calculates a switching fre-

quency that is within +/- 20% of the actual SYNC input

frequency.

If RT is not detected at startup, the IC logs an RT fault

error in 0x00h [6:5]. The RT value cannot be changed

after startup.

When using an external clock at the SYNC pin, dynamic

changes of the external input clock, for example, exter-

nal spread-spectrum, is only supported for the range of

±20% from the target switching frequency set by RT.

When using the IC in slave operation, the user should

choose one of the seven RT values in Table 8.

ACT43750 Datasheet(PDF) 32 Page - Qorvo, Inc

ACT43750 Datasheet(HTML) 32 Page - Qorvo, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL