Data Sheet Rev. E August 2021 | Subject to change without notice

23 of 37

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ACT4910

Power Loss Protection with 6A eFuse

®

this configuration, the following equation calculates the

output voltage.

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(10)

Where VBSTVSET is the voltage set by the BSTVSET

register in Table 5 and RBSET is the resistor on the BSET

pin in ohms.

As an example, with BSTVSET[4:0] = 10111 (sets

VBSTVSET = 28V) and RBSET = 34.2k

Ω, VSTR = 12.8V. Note

that RBSET should be set between 20k

Ω and 75kΩ.

Setting RBSET below 20k

Ω gives the same result as

using a 20k

Ω resistor. Setting RBSET above 75kΩ gives

the same result as using a 75k

Ω resistor. Using RBSET

outside the range is acceptable and does not damage

the IC.

Input Capacitor Selection

There are no special considerations for the boost

converter input capacitor. The IC topology uses the

buck converter output capacitor for the boost input

capacitor. Proper selection of the buck converter output

capacitor automatically results in an acceptable boost

converter input capacitor.

Output Inductor Selection

There are no special considerations for the boost

converter inductor. The IC topology uses the buck

converter inductor for the boost converter inductor.

Proper selection of the buck converter output capacitor

automatically results in an acceptable boost converter

input capacitor.

Output Capacitor Selection

The IC topology uses the buck converter input capacitor

for the boost converter output capacitor. Note that the

storage capacitors are also included in the boost

converter output capacitors. Proper selection of the

buck converter input capacitor typically results in an

acceptable boost converter output capacitor. The boost

output capacitor has two criteria. The first is that it must

consist of at least 10µF of high quality X5R or X7R

ceramic capacitance placed directly between the STR

pin and PGND. The second criteria is that the sum of

the ceramic capacitor and storage capacitors must be

greater than 100µF. There is no requirement for the

additional capacitance dielectric material. This provides

flexibility for the storage capacitors, which allows the

use of super capacitors, electrolytic, polymer, Tantalum,

ceramic, or any capacitors in the design.

Output Voltage UVLO Setting

The storage capacitor power good signal indicates that

the STR voltage is above the UVLO threshold. The

UVLO threshold is shared with the storage capacitor

health check, and is set by the I2C register HMON_THR

[3:0]. The default value is determined by the IC’s

specific CMI option.

Table 6: Storage Capacitor PG Threshold

HMON_THR[2:0]

HMON_THR[3]

0

1

000

95.0%

96.6%

001

95.2%

96.8%

010

95.4%

97.0%

011

95.6%

97.2%

100

95.8%

97.4%

101

96.0%

97.6%

110

96.2%

97.8%

111

96.4%

98.0%

STORAGE CAPACITOR HEALTH

MONITOR

General Description

The ACT4910 has an internal health monitor for the

storage capacitors. It applies a constant current sink to

the capacitors and monitors the voltage drop. If the

voltage drops below a predetermined threshold, the IC

asserts nIRQ to indicate that the storage capacitance

has dropped below the allowable threshold. Health

monitoring is completely autonomous, but can also be

manually initiated by the system uP. Health monitoring

can also be configured so that it is only a manual

operation so it can be triggered on demand to avoid any

critical

system

operations.

The

health

monitor

parameters are adjustable via I2C registers to allow

flexibility for different capacitor values.

Health Monitor Algorithm

The health check algorithm sinks 10mA into the STR pin

for a time determined by I2C register HMON_TSET. It

then sinks 50mA for 200us. It monitors the voltage on

the STR pin, and if the voltage drops more than the

percentage set by I2C register HMON_THR, it asserts

nIRQ low and sets the fault bit. The IC’s specific CMI

option sets the default HMON_TSET and HMON_THR

settings. After the HMON_TSET time, the boost turns

back on to recharge the storage capacitor.