ACT4910 datasheet(5/37 Pages) QORVO

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Data Sheet Rev. E August 2021 | Subject to change without notice

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ACT4910

Power Loss Protection with 6A eFuse

PIN DESCRIPTIONS

NAME

DESCRIPTION

HSB

High Side Bias, Boot-strap pin. This provides power to the internal high-side MOSFET gate

driver circuitry. Connect a 47nF capacitor from HSB pin to SW pin

PLI

Power Loss Indicator Open-Drain Output. PLI goes low to indicate loss of input power.

Can also be configured as a storage voltage monitor or an output voltage monitor. PLI is

referenced to VSS.

3, 28

PGND

Power Ground. Connect to large ground plane on PCB

BSET

Sets the storage capacitor voltage. Place a resistor from BSET to VSS to set the desired

voltage.

REF

5V Internal Bias Voltage Output. Connect a 1µF capacitor between REF and VSS. REF is for

internal use only. Do not connect any circuitry to REF.

COMP

Compensation input pin for the buck converter.

Output Voltage Feedback. Kelvin connect FB to the output capacitor.

VSS

Analog Ground. Kelvin connect VSS to the PGND plane.

SCL

I2C Clock Input. Needs an external pull up resistor.

SDA

I2C Data Input and Output. Needs an external pull up resistor.

11,12,13,23, 24, 25

VOUT

Output for by-pass mode, in-rush, and eFuse functionality. Connect VOUT to the system load.

nIRQ

Interrupt Open-Drain Output. nIRQ goes low to indicate a fault condition. nIRQ is referenced

to VSS.

ISET

Input and Output Current Limit pin. ISET can also indicate the load current through the eFuse.

Connect a resistor from ISET to VSS to set the current limit.

Soft Start Input. Place a capacitor from SS to VSS to control the eFuse startup voltage slew

rate.

Enable Input. A dual comparator on EN measures the input voltage to determine if it is under,

voltage, over voltage, or within normal operating limits. Connect a resistive voltage divider

between VIN, EN, and VSS to set the EN_UV and EN_UV thresholds. The EN_UV threshold is

0.64V. The EN_OV threshold is typically 0.92V, but can be modified by the IC’s CMI.

18,19, 20, 21, 22

VIN

Power Supply Input. Input to the eFuse. Connect a 0.1µF capacitor between VIN and PGND as

close to the IC as possible.

STR

Storage Capacitor Input. Connect the storage capacitors to STR. STR requires a minimum

capacitor of 100µF to PGND.

Switching Pin. This is the boost converter switch node and the buck converter switch node.

Connect the inductor to SW.

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