33800 datasheet(35/39 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33800

TYPICAL APPLICATIONS

INTRODUCTION

TYPICAL APPLICATIONS

INTRODUCTION

Output OFF Open Load Fault

An Output OFF Open Load Fault is the detection and

reporting of an open load when the corresponding output is

disabled (input bit programmed to a logic low state). The

Output OFF Open Load Fault is detected by comparing the

drain-to-source voltage of the specific MOSFET output to an

internally generated reference. Each output has one

dedicated comparator for this purpose.

Each output has an internal pull-down current source or

resistor. The pull-down current sources are enabled on

power-up and must be enabled for Open Load Detect to

function. In cases were the Open Load Detect current is

disabled, the status bit will always respond with logic 0. The

device will only shut down the pull-down current in Sleep

Mode or when disabled via the SPI.

During output switching, especially with capacitive loads,

a false Output OFF Open Load Fault may be triggered. To

prevent this false fault from being reported, an internal fault

filter of 100µs to 450µs is incorporated. The duration for

which a false fault may be reported is a function of the load

impedance, RDS(ON), COUT of the MOSFET, as well as the

supply voltage, VPWR. The rising edge of CS triggers the built-

in fault delay timer. The timer must time out before the fault

comparator is enabled to detect a faulted threshold. Once the

condition causing the Open Load Fault is removed, the

device resumes normal operation. The Open Load Fault,

however, will be latched in the output SO Response register

for the MCU to read.

Under-voltage Shutdown

An under-voltage condition on VDD results in the global

shutdown of all outputs and reset of all control registers. The

under-voltage threshold is between 0.8 and 2.8V.

An under-voltage condition on VPWR also results in the

global shutdown of all outputs and reset of all control

registers. The under-voltage threshold is between 3.0 and

4.4V

Low-voltage condition (4.4V< VPWR <9.0V) will operate

per the command word, however status reported on SO pin

is not guaranteed and performance may be out of

specification limits.

Output Voltage Shutdown

An over voltage condition on VDD (> 7.0) may result in

permanent damage to the 33800. Over-voltage on the VPWR

pin will cause the 33800 to shut down until the voltage returns

to a normal value. Over voltage exceeding the maximum

recommended voltage (45V) may cause permanent damage

to the 33800.

Output Voltage Clamp

Each output of the 33800 incorporates an internal voltage

clamp to provide fast turn-OFF and transient protection of

each output. Each clamp independently limits the drain-to-

source voltage to 50V. The total energy clamped (EJ) can be

calculated by multiplying the current area under the current

curve (IA) times the clamp voltage (VCL) (see Figure 10).

Characterization of the output clamps, using a single pulse

non-repetitive method at 0.3A, indicates the maximum

energy to be 50mJ at 150

°C junction temperature per output.

Figure 10. Output Voltage Clamping

Reverse Battery Protection

The 33800 device requires external reverse battery

protection on the VPWR pin.

All outputs consist of a power MOSFET with an integral

substrate diode. During reverse battery condition, current will

flow through the load via the substrate diode. Under this

circumstance relays may energize and lamps will turn on. If

load reverse battery protection is desired, a diode must be

placed in series with the load.

Curren t

Area (IA )

Clamp Energy

= I

x V

)

Drain Voltage

Time

Dr ain-to-Source C lamp

Voltage (VCL = 45 V)

Drain Current

= 0.3 A)

GND

Dr ain-to-Source ON

Voltage (VDS (O N))

50V)

Drain-to-Source Clamp

Voltage (VCL = 50V)

Drain-to-Source ON

Voltage (VDS(ON))

Drain Voltage

Clamp Energy

(EJ = IA x VCL)

GND

Time

Drain Current

(ID = 0.3A)

33800 Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc

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