33800 datasheet(16/39 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33800

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

ANALOG VOLTAGE SUPPLY (VPWR)

The VPWR pin is battery input to the 33800 IC. The VPWR

pin requires external reverse battery and transient protection.

Maximum input voltage on VPWR is 45V. All IC analog

current and internal logic current is provided from the VPWR

pin. With VDD and EN applied to the IC, the application of

VPWR will perform a Power-ON Reset (POR).

DIGITAL VOLTAGE SUPPLY (VDD)

The VDD input pin is used to determine communication

logic levels between the microprocessor and the 33800

device. Current from VDD is used to drive SO output and pull-

up current for CS. VDD must be applied for Normal Mode

operation. Removing VDD from the IC will place the device in

Sleep Mode. Power-ON Reset will be performed with the

application of VDD supply.

GROUND (GND)

The GND pin provides a low current analog ground for the

IC. The VPWR and VDD supplies are both referenced to the

GND pin. GND pin should be used for decoupling both

supplies.

CONSTANT CURRENT DRIVER GROUND

(CCDX_GND)

The Constant Current Driver Ground (CCDX_GND) pins

provide dedicated grounds for the Constant Current output

drivers. Both CCDX_GND1 and CCDX_GND2 grounds are

isolated from the other grounds of the IC.

GROUND (PGND1 - 3, CCD1_GND, CCD2_GND)

There are three PGND pins associated with the OSS

drivers. OUT1 driver and OUT2 driver have dedicated

PGND1 & PGND2 pins. Drivers OUT3 through Driver OUT8

share one PGND3 pin. In general all ground pins must be

connected together and terminated to ground on the circuit

board.

SOURCE VOLTAGE SENSE (VSSNS123,

VSSNS456)

The Source Sense Ground pins (VSSNS123, VSSNS456)

provide dedicated grounds for the hex MOSFET pre-drivers.

The pins are used by the IC to monitor the drain to source

voltage of the external MOSFET. This pin must be connected

to the source of the external MOSFET and system ground.

VSSNS123 and VSSNS456 ground pins are isolated from

other internal IC grounds.

SERIAL CLOCK INPUT (SCLK)

The system clock (SCLK) pin clocks the internal shift

shift register on the rising edge of SCLK signal. The SO pin

shifts status bits out on the falling edge of SCLK. The SO data

is available for the MCU to read on the rising edge of SCLK.

With CS in a logic high state, signals on the SCLK and SI pins

will be ignored and the SO pin is tri-state.

CHIP SELECT (CS)

The system MCU selects the 33800 to receive

communication using the chip select (CS) pin. With the CS in

a logic low state, command words may be sent to the 33800

via the serial input (SI) pin, and status information is received

by the MCU via the serial output (SO) pin. The falling edge of

CS enables the SO output and transfers status information

into the SO buffer.

Rising edge of the CS initiates the following operation:

1. Disables the SO driver (high-impedance)

2. Activates the received command word, allowing the

33800 to activate/deactivate output drivers.

To avoid any spurious data, it is essential the high-to-low

and low-to-high transitions of the CS signal occur only when

SCLK is in a logic low state. Internal to the 33800 device is an

active pull-up to VDD on CS. In cases were voltage exists on

CS without the application of VDD, no current will flow from

CS to the VDD pin.

SERIAL INPUT DATA (SI)

The SI pin is used for serial instruction data input. SI

information is latched into the input register on the rising edge

of SCLK. A logic high state present on SI will program a one

in the command word on the rising edge of the CS signal. To

program a complete word, 16-bits of information must be

entered into the device.

SERIAL OUTPUT DATA (SO)

The SO pin is the output from the shift register. The SO pin

remains tri-stated until the CS pin transitions to a logic low

state. All normal operating drivers are reported as zero, all

faulted drivers are reported as one. The negative transition of

CS enables the SO driver.

The SI/SO shifting of the data follows a first-in-first-out

protocol, with both input and output words transferring the

most significant bit (MSB) first.

ENABLE (EN)

The ENABLE pin is an active high digital input pin used to

enable the device. With the EN pin low the device is in Sleep

Mode. With the EN pin high, the device is in Normal Mode

(VDD and VPWR applied). Exit from Sleep Mode initiates a

33800 Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc

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