33800 datasheet(19/39 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33800

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

POWER SUPPLY

The 33800 is designed to operate from 5.0 to 36V on the

VPWR pin. The VPWR pin supplies power to all internal

regulators, analog and logic circuit blocks. The VDD supply is

used for setting communication threshold levels and

supplying power to the SO driver. This IC architecture

provides flexible microprocessor interfacing with low

quiescent current Sleep Modes.

POWER-ON RESET (POR)

Applying VPWR, VDD and EN to the device will cause a

Power On Reset (POR) and place the device in Normal or

Default Mode.

Command register settings from Power-ON Reset (POR)

via VPWR or VDD are as follows:

• All Outputs Off

• Inputs Enabled and OR’d with SPI Bit.

• PWM Frequency and Duty Cycle Control Disabled.

• OSS Open Load Detect Current Enabled.

• OSS Outputs with Individual Control.

• Control Inputs P1,P3,P5,P7 Enabled and OR’d with the

SPI Bit.

• CCD1 Output Off, Diagnostic Pull-up Enabled, DAC = 0.

• CCD2 Output Off, Diagnostic Pull-up Enabled, DAC = 0.

Power On Reset circuit incorporates a 0.5µs timer to

prevent high frequency transients from causing a POR.

During the low-voltage condition, internal logic states are

maintained. To guarantee a POR from VPWR, the VPWR pin

must be less than 0.2V for greater than 1.0µs.

MODES OF OPERATION

The 33800 has three operating modes, Normal, Sleep and

Default Mode. A discussion on Normal Mode follows.

NORMAL MODE

Normal Mode allows full functional control of the device.

Transferring from Sleep Mode to Normal Mode performs a

POR and resets all internal registers to the POR state. When

entering Normal Mode from Default Mode, no POR is

performed and register states are maintained.

Features programmed in Normal Mode are listed below.

Further explanation of each feature is provided in subsequent

paragraphs.

• Programmable PWM Frequency & Duty Cycle

• Programmable PWM Drain Fault Threshold

• CCD2 Constant Current Dither Frequency and Amplitude

• CCD2 DAC Programming

• CCD1 Constant Current Dither Frequency and Amplitude

• CCD1 DAC Programming

• On/Off OSS Open Load Detect Current

• Calibration of Timers (Calibration Command)

•Reset (Reset Command)

• No Operation (NO_OP Command)

DEFAULT MODE

The Default Mode allows the user to disable all outputs

except the PWM pre-driver. In Default Mode the PWM pre-

driver outputs may only be controlled via the PWM input pins.

All register control bits and fault bits are maintained in Default

Mode, however control for the pre-driver is accomplished

through the PWM pins only.

With the DEFAULT pin HIGH, the device is placed in

Default Mode. When exiting Default Mode, output control

reverts to the internal register settings.

In Default Mode the device operates with the following

parameters.

1. OSS outputs are disabled.

2. CCD1 and CCD2 outputs are disabled.

3. SPI ON/OFF control of GATE DRIVE (GD1 to GD6)

outputs is disabled. PWMx input control is enabled. The

device will operate as programmed prior to Default Mode.

In Default Mode the device retains all register information

and output status information. Normal operation will resume

when the DEFAULT pin transitions low again.

SLEEP MODE

Sleep Mode is entered by placing a logic [0] on the

ENABLE or VDD pins. All outputs are commanded off and the

device enters a low quiescent current state.

Table 5. Modes of Operation

VPWR

VDD

ENable

DEFAULT

MODE

Power

Off

SLEEP

NORMAL

DEFAULT

33800 Datasheet(PDF) 19 Page - Freescale Semiconductor, Inc

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