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33800 Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc |
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33800 Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 39 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 13 33800 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS OCTAL SERIAL DRIVERS (OUT1 - OUT8) (CONTINUED) Output Off Open Circuit Fault Filter Timer(11) tOC 400 500 650 µs Output Slew Rate RLOAD = 51Ω RLOAD = 51Ω tSR(RISE) tSR(FALL) 1.0 1.0 5.0 5.0 10 10 V/ µs P1 Input Propagation Delay Input @ 50% VDD to Output voltage 10% of final value Input @ 50% VDD to Output voltage 90% of initial value t(RISEDELAY) t(FALLDELAY) 6.0 6.0 µs P3, P5, P7 Input Propagation Delay Input @ 50% VDD to Output voltage 10% of final value Input @ 50% VDD to Output voltage 90% of initial value t(RISEDELAY) t(FALLDELAY) 5.0 5.0 µs OSCILLATOR AND TIMER ACCURACY Calibrated Timer Accuracy(11) tTIMER – – ±10 % Un-calibrated Timer Accuracy tTIMER – – ±80 % SPI DIGITAL INTERFACE TIMING (SO, SI, CS, SCLK)(12) Required Low State Duration on VPWR for Reset (13) VPWR ≤ 0.2V tRESET 1.0 – – µs Falling Edge of CS to Rising Edge of SCLK Required Setup Time tLEAD 100 – – ns Falling Edge of SCLK to Rising Edge of CS Required Setup Time tLAG 50 – – ns SI to Rising Edge of SCLK Required Setup Time tSI(SU) 16 – – ns Rising Edge of SCLK to SI Required Hold Time tSI(HOLD) 20 – – ns SI, CS, SCLK Signal Rise Time(14) tR(SI) – 5.0 – ns SI, CS, SCLK Signal Fall Time(14) tF(SI) – 5.0 – ns Time from Falling Edge of CS to SO Low-impedance(15) tSO(EN) – – 150 ns Time from Rising Edge of CS to SO High-impedance(16) tSO(DIS) – – 150 ns Time from Falling Edge of SCLK to SO Data Valid(17) tVALID – 25 150 ns Sequential Transfer Rate Time required between data transfers tSTR 1.0 µs Notes 11. Assumes oscillator has been calibrated using SPI Calibrate Command 12. These parameters are guaranteed by design. Production test equipment uses 1MHz, 5.0V SPI interface. 13. This parameter is guaranteed by design, however it is not production tested. 14. Rise and Fall time of incoming SI, CS, and SCLK signals for design consideration to prevent the occurrence of double pulsing. 15. Time required for valid output status data to be available on SO pin. 16. Time required for output states data to be terminated at SO pin. 17. Time required to obtain valid data out from SO following the fall of SCLK with 200pF load. Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 3.0V ≤ V DD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit |
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