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TIMING DIAGRAMS

Analog

Input

CLK

DATA[D9:D0]

DV

OE

DATA

D9:D0

t

OE

t

OE

t

DV

t

1

t

2

t

C

t

A

N+1

N+2

N+4

N+3

N

TIMING CHARACTERISTICS

(1)

ADS5237

SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007

cycle, and total capacitive loading = 10pF, unless otherwise noted.

PARAMETER

MIN

TYP

MAX

UNITS

65MSPS With PLL ON

2.1

ns

Aperture jitter

1.0

ps

(2)

2

3.2

ns

(3)

6.3

8.5

ns

6

Clocks

(4)

0.5

2

3

ns

Data valid (DV) duty cycle

30

40

55

%

10

11.5

14

ns

(1)

Specifications assured by design and characterization; not production tested.

(2)

Measured from data becoming valid (at a high level = 2.0V and a low level = 0.8V) to the 50% point of the falling edge of DV.

(3)

Measured from the 50% point of the falling edge of DV to the data becoming invalid.

(4)

Measured between 20% to 80% of logic levels.

Copyright © 2007, Texas Instruments Incorporated

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