ADS5237 datasheet(21/29 Pages) TI

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External Reference

SNR=20Log

(2 f t )

p IN JA

(1)

PLL CONTROL

OUTPUT INFORMATION

CLOCK INPUT

ADS5237

SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007

IF-sampling applications; for example, where the

sampling frequency is lower than the input frequency

The ADS5237 also supports the use of external

(under-sampling). The following equation can be used

reference voltages. External reference voltage mode

to calculate the achievable SNR for a given input

involves applying an external top reference at REFT

frequency and clock jitter (tJA in psRMS):

(pin 53) and a bottom reference at REFB (pin 54).

Setting the ADS5237 for external reference mode

also requires taking the INT/EXT pin low. In this

mode, the internal reference buffer is 3-stated.

The ADS5237 enters into a power-down mode if the

Because the switching current for the two ADC

sampling

clock

rate

drops

below

limit

channels

comes

from

the

externally-forced

approximately

2MSPS.

the

sampling

rate

references, it is possible for the device performance

increased

above

this

threshold,

the

ADS5237

to be slightly lower than when the internal references

automatically resumes normal operation.

are used. It should be noted that in external reference

mode, VCM and ISET continue to be generated from

the internal bandgap voltage, as they are in the

internal reference mode. Therefore, it is important to

The ADS5237 has an internal PLL that is enabled by

ensure

that

the

common-mode

voltage

the

default. The PLL enables a wide range of clock duty

externally-forced

reference

voltages

matches

cycles. Good performance is obtained for duty cycles

within 50mV of VCM (+1.5VDC).

up to 40%–60%, though the ensured electrical

specifications presume that the duty cycle is between

The external reference circuit must be designed to

45%–55%. The PLL automatically limits the minimum

drive the internal reference impedance seen between

frequency of operation to 20MSPS. For operation

the REFT and REFB pins. To establish the drive

below 20MSPS, the

PLL

can

disabled

requirements, consider that the external reference

programming the internal registers through the serial

circuit needs to supply an average switching current

interface. With the PLL disabled, the clock speed can

of at least 1mA. This dynamic switching current

go down to 2MSPS. With the PLL disabled, the clock

depends on the actual device sampling rate and the

duty cycle needs to be constrained closer to 50%.

signal level. The external reference voltages can vary

as long as the value of the external top reference

stays within the range of +1.875V to +2.0V, and the

external bottom reference stays within +1.0V to

The ADS5237 provides two channels with 10 data

+1.125V. Consequently, the full-scale input range can

outputs (D9 to D0, with D9 being the MSB and D0 the

be set between 1.5VPP and 2VPP (FSR = 2x [REFT –

LSB), data-valid outputs (DVA, DVB, pin 26 and pin

REFB] ).

22, respectively), and individual out-of-range indicator

output

pins

(OVRA/OVRB, pin 39 and pin 9,

respectively).

The ADS5237 requires a single-ended clock source.

The output circuitry of the ADS5237 has been

The clock input, CLK, represents a CMOS-compatible

designed

minimize

the

noise

produced

logic input with an input impedance of about 5pF. For

transients of the data switching, and in particular its

high input frequency sampling, it is recommended to

coupling to the ADC analog circuitry.

use a clock source with very low jitter. A low-jitter

clock is essential in order to preserve the excellent ac

performance of the ADS5237. The converter itself is

specified for a low 1.0ps (rms) jitter. Generally, as the

input frequency increases, clock jitter becomes more

dominant in maintaining a good signal-to-noise ratio

(SNR).

This

condition

particularly

critical

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