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POWER-DOWN MODE

ADS5237

SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007

reference voltages settle to within 1% of their

The ADS5237 has a power-down pin, STPD (pin 45).

steady-state values in less than 500

μs. Either of the

The internal pull-down is in default mode for the

two channels can also be selectively powered-down

device during normal operation. Forcing the STPD pin

through the serial interface when it is enabled.

high causes the device to enter into power-down

mode. In power-down mode, the reference and clock

The ADS5237 also has an internal circuit that

circuitry as well as all the channels are powered

monitors the state of stopped clocks. If ADCLK is

down. Device power consumption drops to less than

stopped for longer than 250ns, or if it runs at a speed

90mW. As previously mentioned, the ADS5237 also

less than 2MHz, this monitoring circuit generates a

enters into a power-down mode if the clock speed

logic signal

that

puts

the

device

in

a

partial

drops below 2MSPS (see the Clock Input section).

power-down

state.

As

a

result,

the

power

consumption of the device is reduced when CLK is

When STPD is pulled high, the internal buffers driving

stopped.

The

recovery

from

such

a

partial

power-down

takes

approximately

100

μs.

This

forced to a voltage roughly equal to half of the

constraint is described in Table 4.

power-down mode depends on the value of the

Table 4. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage

DESCRIPTION

TYP

REMARKS

Recovery from power-down mode (STPD = 1 to STPD = 0).

500

μs

Recovery from momentary clock stoppage ( < 250ns).

10

μs

Recovery from extended clock stoppage ( > 250ns).

100

μs

Copyright © 2007, Texas Instruments Incorporated

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