ADS5237 datasheet(24/29 Pages) TI

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LAYOUT AND DECOUPLING

ADS5237

SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007

the lead and trace inductance, the capacitors should

CONSIDERATIONS

be located as close to the supply pins as possible.

Where double-sided component mounting is allowed,

Proper grounding and bypassing, short lead length,

they are best placed directly under the package. In

and the use of ground planes are particularly

addition, larger bipolar decoupling capacitors (2.2

μF

important for high frequency designs. Achieving

to 10

μF), effective at lower frequencies, may also be

optimum performance with a fast sampling converter

used on the main supply pins. They can be placed on

such as the ADS5237 requires careful attention to the

the PCB in proximity (< 0.5in) to the ADC.

PCB layout to minimize the effects of board parasitics

and to optimize component placement. A multilayer

If the analog inputs to the ADS5237 are driven

board usually ensures best results and allows

differentially, it is especially important to optimize

convenient component placement.

towards a highly symmetrical layout. Small trace

length

differences

may

create

phase

shifts,

The ADS5237 should be treated as an analog

compromising a good distortion performance. For this

component and the supply pins connected to clean

reason, the use of two single op amps rather than

analog supplies. This layout ensures the most

one dual amplifier enables a more symmetrical layout

consistent

performance

results,

because

digital

and a better match of parasitic capacitances. The pin

supplies often carry a high level of switching noise

orientation of the ADS5237 quad-flat package follows

that could couple into the converter and degrade

a flow-through design, with the analog inputs located

device performance. As mentioned previously, the

on one side of the package while the digital outputs

output buffer supply pins (VDRV) should also be

are located on the opposite side. This design

connected to a low-noise supply. Supplies of adjacent

provides a good physical isolation between the

digital

circuits

may

carry

substantial

current

analog and digital connections. While designing the

transients. The supply voltage should be filtered

layout, it is important to keep the analog signal traces

before connecting to the VDRV pin of the converter.

separated from any digital lines to prevent noise

All ground pins should directly connect to an analog

coupling onto the analog portion.

ground.

Single-ended clock lines must be short and should

Because

its

high

sampling

frequency,

the

not cross any other signal traces.

ADS5237 generates high frequency current transients

and noise (clock feedthrough) that are fed back into

Short circuit traces on the digital outputs will minimize

the supply and reference lines. If not sufficiently

capacitive loading. Trace length should be kept short

bypassed,

this

feedthrough

adds

noise

the

to the receiving gate (< 2in) with only one CMOS gate

conversion process. All AVDD pins may be bypassed

connected to one digital output.

with 0.1

μF ceramic chip capacitors (size 0603, or

smaller). A similar approach may be used on the

output buffer supply pins, VDRV. In order to minimize

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