ADS5237 datasheet(18/29 Pages) TI

18 / 29 page

www.ti.com

APPLICATION INFORMATION

THEORY OF OPERATION

INPUT CONFIGURATION

INPUT DRIVER CONFIGURATIONS

Transformer-Coupled Interface

ADS5237

SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007

The

ADS5237

dual-channel,

simultaneous

The analog input for the ADS5237 consists of a

sampling analog-to-digital converter (ADC). Its low

differential sample-and-hold architecture implemented

power and high sampling rate of 65MSPS are

using a switched capacitor technique; see Figure 17.

achieved using a state-of-the-art switched capacitor

The sampling circuit consists of a low-pass RC filter

pipeline architecture built on an advanced low-voltage

at the input to filter out noise components that

CMOS process. The ADS5237 operates from a +3.3V

potentially could be differentially coupled on the input

supply voltage for both its analog and digital supply

pins. The inputs are sampled on two 4pF capacitors.

connections. The ADC core of each channel consists

The RLC model is illustrated in Figure 17.

of a combination of multi-bit and single-bit internal

pipeline stages. Each stage feeds its data into the

digital

error

correction

logic,

ensuring

excellent

differential linearity and no missing codes at the

10-bit level. The conversion process is initiated by the

If the application requires a signal conversion from a

rising edge of the external clock. Once the signal is

single-ended

source

drive

the

ADS5237

captured by the input sample-and-hold amplifier, the

differentially, an RF transformer could be a good

input sample is sequentially converted within the

solution. The selected transformer must have a

pipeline stages. This process results in a data latency

center tap in order to apply the common-mode dc

of six clock cycles, after which the output data is

voltage (VCM) necessary to bias the converter inputs.

available as a 10-bit parallel word, coded in either

AC grounding the center tap generates the differential

straight

offset

binary

(SOB)

binary

two's

signal swing across the secondary winding. Consider

complement (BTC) format. Because a common clock

a step-up transformer to take advantage of signal

controls the timing of both channels, the analog

amplification without the introduction of another noise

signal is sampled simultaneously. Data on the parallel

source. Furthermore, the reduced signal swing from

ports are updated simultaneously as well. Further

the

source

may

lead

improved

distortion

processing can be timed using the individual data

performance. The differential input configuration may

valid output signal of each channel. The ADS5237

provide a noticeable advantage for achieving good

features internal references that are trimmed to

SFDR performance over a wide range of input

ensure a high level of accuracy and matching. The

frequencies. In this mode, both inputs (IN and IN) of

internal references can be disabled to allow for

the ADS5237 see matched impedances.

external reference operation.

Figure 18 illustrates the schematic for the suggested

transformer-coupled interface circuit. The component

values of the RC low-pass filter may be optimized,

depending on the desired roll-off frequency.

Submit Documentation Feedback

Product Folder Link(s): ADS5237

ADS5237 Datasheet(PDF) 18 Page - Texas Instruments

ADS5237 Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL