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TLK6002 Datasheet(PDF) 57 Page - Texas Instruments |
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TLK6002 Datasheet(HTML) 57 Page - Texas Instruments |
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57 / 98 page ![]() TLK6002 www.ti.com SLLSE34A – MAY 2010 – REVISED AUGUST 2010 Table 3-22. LATENCY_COUNTER_2 Address: 0x11 Default: 0x0000 BIT(s) NAME DESCRIPTION ACCESS Comma indication for the current latency measurement. Cleared when Register 0x12 is read 17.15 LATENCY_MEAS_TX_COMMA 0 = Indicates Latency measurement detected comma on TXD[19:10] 1 = Indicates Latency measurement detected comma on TXD[9:0] Comma indication for the current latency measurement. Cleared when Register 0x12 is read 17.14 LATENCY_MEAS_RX_COMMA RO/LH(1) 0 = Indicates Latency measurement detected comma on RXD[19:10] 1 = Indicates Latency measurement detected comma on RXD[9:0] Latency measurement ready indicator 0 = Indicates latency measurement not complete. 17.4 LATENCY_ MEAS_READY 1 = Indicates latency measurement is complete and value in latency measurement counter (LATENCY_MEAS_COUNT[19:0]) is ready to be read. Bits[19:16] of 20 bit wide latency measurement counter. Latency measurement counter value represents the latency in number of clock 17.3:0 LATENCY_MEAS_COUNT[19:16] cycles. This counter will return 20’h00000 if it is read before rx comma is COR(1) received. If latency is more than 20’hFFFFF clock cycles then this counter returns 20’hFFFFF. (1) User has to make sure Register 0x11 has to be read first before reading Register 0x12. Latency measurement counter value resets to 20’h00000 when Register 0x12 is read. Comma indication (17.15 and 17.14) and count valid (17.4) bits are also cleared when Register 0x12 is read. Table 3-23. LATENCY_COUNTER_1 Address: 0x12 Default: 0x0000 BIT(s) NAME DESCRIPTION ACCESS 18.15:0 LATENCY_MEAS_COUNT[15:0] Bits[15:0] of 20 bit wide latency measurement counter. COR(1) (1) User has to make sure Register 0x11 has to be read first before reading Register 0x12. Latency measurement counter value resets to 20’h00000 when Register 0x12 is read. Comma indication (17.15 and 17.14) and count valid (17.4) bits are also cleared when Register 0x12 is read. Table 3-24. TI_RESERVED_CONTROL_1 Address: 0x13 Default: 0x0200 BIT(s) NAME DESCRIPTION ACCESS 19.12 RESERVED For TI use only 19.9 RESERVED For TI use only 19.8 RESERVED For TI use only N/A 19.7 RESERVED For TI use only 19.3 RESERVED For TI use only 19.0 RESERVED For TI use only Copyright © 2010, Texas Instruments Incorporated PROGRAMMERS REFERENCE 57 Submit Documentation Feedback Product Folder Link(s): TLK6002 |
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