TLK6002 datasheet(76/98 Pages) TI2

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TLK6002

SLLSE34A – MAY 2010 – REVISED AUGUST 2010

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4.18 Device Initialization

The following subsections provide proper provisioning sequences for various TLK6002 operating modes

using the MDIO interface. Please note that the provisioning method for optimal serial link performance is

dependent on system characteristics such as the length of an electrical cable or printed circuit board trace

connected to the serial interface. For long electrical serial links such as long backplane and cable

channels, the standard MDIO provisioning method is preferred. For short electrical serial links such as

between the SERDES and an optical module, the STCI-via-MDIO provisioning method is preferred. The

STCI-via-MDIO provisioning method provides a way to further fine-tune the serial link performance. The

STCI-via-MDIO provisioning method is described in detail in the “TLK6002 Provisioning for Optimal Serial

Link Performance” application note.

4.18.1 20-Bit Interface Mode (8b/10b Encoder/Decoder Disabled) (All CPRI/OBSAI Rates)

Note: Assume both channel A and channel B have the same setup.

REFCLK frequency = 122.88 MHz, Mode = Transceiver, Parallel Interface = 20-Bit SDR Falling Edge

Aligned Mode, RXCLK_A/B out = RXBCLK_A/B, Serial Data Rate is CPRI/OBSAI standard rate as shown

below.

•

Device Pin Setting(s) – Pin settings allow for maximum software configurability.

–

Ensure CODEA_EN input pin is Low.

–

Ensure CODEB_EN input pin is Low.

–

Ensure RATE_A[2:0] input pins are 3’b100 (High, Low, Low) to enable software control.

–

Ensure RATE_B[2:0] input pins are 3’b100 (High, Low, Low) to enable software control.

–

Ensure PD_TRXA_N input pin is High.

–

Ensure PD_TRXB_N input pin is High.

–

Ensure PRBS_EN input pin is Low.

–

Ensure REFCLK_A_SEL input pin is Low to enable software control.

–

Ensure REFCLK_B_SEL input pin is Low to enable software control.

•

Reset Device

–

Issue a hard or soft reset (RESET_N asserted for at least 10 µs -or- Write 1’b1 to 0.15

GLOBAL_RESET) after power supply stabilization.

•

Enable MDIO global write so that each MDIO write affects both channels to shorten provisioning time

–

Write 1’b1 to 0.11 GLOBAL_WRITE

•

Clock Configuration

–

Select Channel A SERDES REFCLK input (Default = REFCLK_0_P/N)

•

If REFCLK_0_P/N used – Write 1’b0 to 0.1 REFCLK_A_SEL

•

If REFCLK_1_P/N used – Write 1’b1 to 0.1 REFCLK_A_SEL

–

Select Channel B SERDES REFCLK input (Default = REFCLK_0_P/N)

•

If REFCLK_0_P/N used – Write 1’b0 to 0.0 REFCLK_B_SEL

•

If REFCLK_1_P/N used – Write 1’b1 to 0.0 REFCLK_B_SEL

•

Data Rate Setting (select one of the following 8 cases)

–

If serial data rate is 6144.00Mbps: write 2’b00 to 1.7:6 RATE_TX[1:0], write 2’b00 to 1.5:4

RATE_RX[1:0], write 4’b1110 to 1.3:0 PLL_MULT[3:0] to select FULL rate and 25x MPY

(CHANNEL_CONTROL_1 = 0x010E).

–

If serial data rate is 4915.20Mbps: Write 2’b00 to 1.7:6 RATE_TX[1:0], write 2’b00 to 1.5:4

RATE_RX[1:0], write 4’b1101 to 1.3:0 PLL_MULT[3:0] to select FULL rate and 20x MPY

(CHANNEL_CONTROL_1 = 0x010D).

–

If serial data rate is 3072.00Mbps: Write 2’b01 to 1.7:6 RATE_TX[1:0], write 2’b01 to 1.5:4

RATE_RX[1:0], write 4’b1110 to 1.3:0 PLL_MULT[3:0] to select HALF rate and 25x MPY

(CHANNEL_CONTROL_1 = 0x015E).

–

If serial data rate is 2457.60Mbps: Write 2’b01 to 1.7:6 RATE_TX[1:0], write 2’b01 to 1.5:4

ELECTRICAL SPECIFICATIONS

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