DRV8353FS datasheet(28/83 Pages) TI2

28 / 83 page

VDRAIN

VCP

1 …F

CPH

Charge

Pump

Control

CPL

47 nF

VDRAIN

Figure 8-12. Charge Pump Architecture

The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply

input. The VGLS linear regulator allows the gate driver to correctly bias the low-side MOSFET gate with respect

to ground. The VGLS linear regulator output is fixed at 14.5 V and further regulated to 11-V on the GLx outputs

during operation. The VGLS regulator supports an output current of 25 mA. The VGLS linear regulator is

monitored for undervoltage to prevent under driver MOSFET conditions. The VGLS linear regulator requires a

X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND.

Since the charge pump output is regulated to VVDRAIN + 10.5 V this allows for VM to be supplied either directly

from the high voltage motor supply (up to 75 V) to support a single supply system or from a low voltage gate

driver power supply derived from a switching or linear regulator to improve the device efficiency or utilize an

externally available power supply. Figure 8-13 and Figure 8-14 show examples of the DRV835xF configured in

either single supply or dual supply configuration.

DRV835xF

VDRAIN

Power

MOSFETs

48-V

Power

Supply

Figure 8-13. Single Supply Example

DRV8350F, DRV8353F

SLVSFV1B – AUGUST 2018 – REVISED AUGUST 2021

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DRV8353FS Datasheet(PDF) 28 Page - Texas Instruments