DRV8353FS datasheet(6/83 Pages) TI2

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7 Specifications

7.1 Absolute Maximum Ratings

at TA = –40°C to +125°C (unless otherwise noted)(1)

MIN

MAX

UNIT

GATE DRIVER

Power supply pin voltage (VM)

–0.3

Voltage differential between ground pins (AGND, BGND, DGND, PGND)

–0.3

0.3

MOSFET drain sense pin voltage (VDRAIN)

–0.3

102

MOSFET drain sense pin voltage slew rate (VDRAIN)

V/µs

Charge pump pin voltage (CPH, VCP)

–0.3

VVDRAIN + 16

Charge-pump negative-switching pin voltage (CPL)

–0.3

VVDRAIN

Low-side gate drive regulator pin voltage (VGLS)

–0.3

Internal logic regulator pin voltage (DVDD)

–0.3

5.75

Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO,

VDS)

–0.3

5.75

Continuous high-side gate drive pin voltage (GHx)

–5(2)

VVCP + 0.3

Transient 200-ns high-side gate drive pin voltage (GHx)

–10

VVCP + 0.3

High-side gate drive pin voltage with respect to SHx (GHx)

–0.3

Continuous high-side source sense pin voltage (SHx)

–5(2)

102

Continuous high-side source sense pin voltage (SHx)

–5(2)

VVDRAIN + 5

Transient 200-ns high-side source sense pin voltage (SHx)

–10

VVDRAIN + 10

Continuous low-side gate drive pin voltage (GLx)

–1.0

VVGLS + 0.3

Transient 200-ns low-side gate drive pin voltage (GLx)

–5.0

VVGLS + 0.3

Gate drive pin source current (GHx, GLx)

Internally limited Internally limited

Gate drive pin sink current (GHx, GLx)

Internally limited Internally limited

Continuous low-side source sense pin voltage (SLx)

–1

Transient 200-ns low-side source sense pin voltage (SLx)

–5

Continuous shunt amplifier input pin voltage (SNx, SPx)

–1

Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)

–5

Reference input pin voltage (VREF)

–0.3

5.75

Shunt amplifier output pin voltage (SOx)

–0.3

VVREF + 0.3

Ambient temperature, TA

–40

125

°C

Junction temperature, TJ

–40

150

°C

Storage temperature, Tstg

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2)

VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum.

This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V.

7.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±1000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±500

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±2000 V may actually have higher performance.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500

V may actually have higher performance.

DRV8350F, DRV8353F

SLVSFV1B – AUGUST 2018 – REVISED AUGUST 2021

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