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DRV8353FS Datasheet(PDF) 4 Page - Texas Instruments |
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DRV8353FS Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 83 page  PIN TYPE(1) DESCRIPTION NAME NO. DRV8350FH DRV8350FS INLB 26 26 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. INLC 28 28 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. MODE 18 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor. NC 21 — NC No internal connection. This pin can be left floating or connected to system ground. nFAULT 17 17 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. nSCS — 21 I Serial chip select. A logic low on this pin enables serial interface communication. SCLK — 20 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. SDI — 19 I Serial data input. Data is captured on the falling edge of the SCLK pin. SDO — 18 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. SHA 6 6 I High-side source sense input. Connect to the high-side power MOSFET source. SHB 11 11 I High-side source sense input. Connect to the high-side power MOSFET source. SHC 14 14 I High-side source sense input. Connect to the high-side power MOSFET source. SLA 8 8 I Low-side source sense input. Connect to the low-side power MOSFET source. SLB 9 9 I Low-side source sense input. Connect to the low-side power MOSFET source. SLC 16 16 I Low-side source sense input. Connect to the low-side power MOSFET source. VCP 4 4 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins. VDRAIN 3 3 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains. VDS 20 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. VGLS 31 31 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins. VM 2 2 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins. (1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain 1 CPL 30 GAIN 2 CPH 29 VDS 3 VM 28 IDRIVE 4 VDRAIN 27 MODE 5 VCP 26 nFAULT 6 GHA 25 AGND 7 SHA 24 VREF 8 GLA 23 SOA 9 SPA 22 SOB 10 SNA 21 SOC Not to scale Thermal Pad Figure 6-3. DRV8353FH RTA Package 40-Pin WQFN With Exposed Thermal Pad Top View 1 CPL 30 nSCS 2 CPH 29 SCLK 3 VM 28 SDI 4 VDRAIN 27 SDO 5 VCP 26 nFAULT 6 GHA 25 AGND 7 SHA 24 VREF 8 GLA 23 SOA 9 SPA 22 SOB 10 SNA 21 SOC Not to scale Thermal Pad Figure 6-4. DRV8353FS RTA Package 40-Pin WQFN With Exposed Thermal Pad Top View Pin Functions—40-Pin DRV8353F Devices PIN TYPE(1) DESCRIPTION NAME NO. DRV8353FH DRV8353FS AGND 25 25 PWR Device analog ground. Connect to system ground. CPH 2 2 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins. DRV8350F, DRV8353F SLVSFV1B – AUGUST 2018 – REVISED AUGUST 2021 www.ti.com 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8350F DRV8353F |
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