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DRV8353FS Datasheet(PDF) 5 Page - Texas Instruments |
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DRV8353FS Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 83 page  PIN TYPE(1) DESCRIPTION NAME NO. DRV8353FH DRV8353FS CPL 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins. DVDD 38 38 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This regulator can source up to 10 mA externally. ENABLE 31 31 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions. GAIN 30 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor. GND 39 39 PWR Device power ground. Connect to system ground. GHA 6 6 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. GHB 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. GHC 16 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. GLA 8 8 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. GLB 13 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. GLC 18 18 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. IDRIVE 28 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. INHA 32 32 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INHB 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INHC 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INLA 33 33 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. INLB 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. INLC 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. MODE 27 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor. nFAULT 26 26 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. nSCS — 30 I Serial chip select. A logic low on this pin enables serial interface communication. SCLK — 29 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. SDI — 28 I Serial data input. Data is captured on the falling edge of the SCLK pin. SDO — 27 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. SHA 7 7 I High-side source sense input. Connect to the high-side power MOSFET source. SHB 14 14 I High-side source sense input. Connect to the high-side power MOSFET source. SHC 17 17 I High-side source sense input. Connect to the high-side power MOSFET source. SNA 10 10 I Shunt amplifier input. Connect to the low-side of the current shunt resistor. SNB 11 11 I Shunt amplifier input. Connect to the low-side of the current shunt resistor. SNC 20 20 I Shunt amplifier input. Connect to the low-side of the current shunt resistor. SOA 23 23 O Shunt amplifier output. SOB 22 22 O Shunt amplifier output. SOC 21 21 O Shunt amplifier output. SPA 9 9 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. SPB 12 12 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. SPC 19 19 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. VCP 5 5 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins. VDRAIN 4 4 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains. VDS 29 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. VGLS 40 40 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins. VM 3 3 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins. VREF 24 24 PWR Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins. (1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain www.ti.com DRV8350F, DRV8353F SLVSFV1B – AUGUST 2018 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DRV8350F DRV8353F |
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