DRV8353FS datasheet(39/83 Pages) TI2

39 / 83 page

VVREF ± 0.3 V

VSO(off)max

VSO(off)min

VREF

VVREF ± 0.25 V

0.25 V

0 V

I × R

SP ± SN

VOFF,

VDRIFT

0.3 V

VSO(range)

Figure 8-29. Unidirectional Current-Sense Regions

8.3.4.3 Amplifier Calibration Modes

To minimize DC offset and drift over temperature, a DC calibration mode is provided and enabled through the

SPI register (CSA_CAL_X). This option is not available on hardware interface devices. When the calibration

setting is enabled the inputs to the amplifier are shorted and the load is disconnected. DC calibration can be

done at any time, even when the half-bridges are operating. For the best results, do the DC calibration during the

switching OFF period to decrease the potential noise impact to the amplifier. A diagram of the calibration mode is

shown below. When a CSA_CAL_X bit is enabled, the corresponding amplifier goes to the calibration mode.

SENSE

!CAL

CAL

OUT

VREF

SOx

Figure 8-30. Amplifier Manual Calibration

In addition to the manual calibration method provided on the SPI devices versions, the DRV835xF family of

devices provide an auto calibration feature on both the hardware and SPI device versions in order to minimize

the amplifier input offset after power up and during run time to account for temperature and device variation.

Auto calibration occurs automatically on device power up for both the hardware and SPI device options. The

power up auto calibration starts immediately after the VREF pin crosses the minimum operational VREF voltage.

50 us should be allowed for the power up auto calibration routine to complete after the VREF pin voltage crosses

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DRV8350F, DRV8353F

SLVSFV1B – AUGUST 2018 – REVISED AUGUST 2021

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DRV8353FS Datasheet(PDF) 39 Page - Texas Instruments