DAC38RF86 datasheet(32/147 Pages) TI2

32 / 147 page

108

414

Log10MHz

-6.3

Frequency

DAC38RF86, DAC38RF96

DAC38RF87, DAC38RF97

SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017

www.ti.com

Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97

Submit Documentation Feedback

A free running clock output is available when field ENDIVCLK in register SRDS_PLL_CFG (8.5.85) is set high. It

runs at a fixed divided-by-80 of the PLL output frequency and can be output on the ALARM pin by setting field

DTEST to “0001” (lanes 0 – 3) or “0010” (lanes 4 – 7) in register DTEST (8.5.76).

8.3.4 SerDes Equalizer

All channels of the DAC38RFxx incorporate an adaptive equalizer, which can compensate for channel insertion

loss by attenuating the low frequency components with respect to the high frequency components of the signal,

thereby reducing inter-symbol interference. Figure 37 shows the response of the equalizer, which can be

expressed in terms of the amount of low frequency gain and the frequency up to which this gain is applied (i.e.,

the frequency of the ’zero’). Above the zero frequency, the gain increases at 6 dB/octave until it reaches the high

frequency gain.

Figure 37. Equalizer Frequency Response

The equalizer can be configured via fields EQ and EQHLD in register SRDS_CFG1 (8.5.86). Table 6 and Table 7

summarize the options. When enabled, the receiver equalization logic analyzes data patterns and transition times

to determine whether the low frequency gain should be increased or decreased. The decision logic is

implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that results

reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively stable

response of the channel. The lock time for the adaptive equalizer is data dependent, and so it is not possible to

specify a generally applicable absolute limit. However, assuming random data, the maximum lock time will be

6x106 divided by the CDR activity level. For field CDR in register SRDS_CFG1 (8.5.86) = 110, the activity level

is 1.5 x 106 UI.

When EQ = 0, finer control of gain boost is available using the EQBOOST IEEE1500 tuning chain field, as shown

in Table 8.

Table 6. Receiver Equalization Configuration

EFFECT

[1-0]

No equalization. The equalizer provides a flat response at the maximum gain. This setting may be

appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than

frequency dependent loss.

Fully adaptive equalization. The zero position is determined by the selected operating rate, and the

low frequency gain of the equalizer is determined algorithmically by analyzing the data patterns and

transition positions in the received data. This setting should be used for most applications.

Precursor equalization analysis. The data patterns and transition positions in the received data are

analyzed to determine whether the transmit link partner is applying more or less precursor

equalization than necessary.

Postcursor equalization analysis. The data patterns and transition positions in the received data are

analyzed to determine whether the transmit link partner is applying more or less post-cursor

equalization than necessary.

DAC38RF86 Datasheet(PDF) 32 Page - Texas Instruments

DAC38RF86 Datasheet(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL