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DAC38RF86 Datasheet(PDF) 69 Page - Texas Instruments |
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DAC38RF86 Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 147 page  69 DAC38RF86, DAC38RF96 DAC38RF87, DAC38RF97 www.ti.com SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017 Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Register Maps (continued) Table 42. Register Summary (continued) Address Reset Acronym Register Name Section 0x29 0x0000 PAP_GAIN_AB PAP path AB Gain Attenuation Step 8.5.31 0x2A 0x0000 PAP_WAIT_AB PAP path AB Wait Time at Gain = 0 8.5.32 0x2B 0x0000 PAP_GAIN_CD PAP path CD Gain Attenuation Step 8.5.33 0x2C 0x0000 PAP_WAIT_CD PAP path CD Wait Time at Gain = 0 8.5.34 0x2D 0x1FFF PAP_CFG_AB PAP path AB Configuration 8.5.35 0x2E 0x1FFF PAP_CFG_CD PAP path CD Configuration 8.5.36 0x2F 0x0000 SPIDAC_TEST1 Configuration for DAC SPI Constant 8.5.37 0x30 0x0000 SPIDAC_TEST2 DAC SPI Constant 8.5.38 0x31 0x0000 Reserved Reserved 0x32 0x0800 GAINAB Gain for path AB 8.5.39 0x33 0x0800 GAINCD Gain for path CD 8.5.40 0x34-0x40 0x0000 Reserved Reserved 0x41 0x0000 JESD_ERR_CNT JESD Error Counter 8.5.41 0x42-0x45 0x0000 Reserved Reserved 0x46 0x0044 JESD_ID1 JESD ID 1 8.5.42 0x47 0x190A JESD_ID2 JESD ID 2 8.5.43 0x48 0x31C3 JESD_ID3 JESD ID 3 and Subclass 8.5.44 0x49 0x0000 Reserved Reserved 0x4A 0x0003 JESD_LN_EN JESD Lane Enable 8.5.45 0x4B 0x1300 JESD_RBD_F JESD RBD Buffer and Frame Octets 8.5.46 0x4C 0x1303 JESD_K_L JESD K and L Parameters 8.5.47 0x4D 0x0100 JESD_M_S JESD M and S Parameters 8.5.48 0x4E 0x0F4F JESD_N_HD_SCR JESD N, HD and SCR Parameters 8.5.49 0x4F 0x1CC1 JESD_MATCH JESD Character Match and Other 8.5.50 0x50 0x0000 JESD_LINK_CFG JESD Link Configuration Data 8.5.51 0x51 0x00FF JESD_SYNC_REQ JESD Sync Request 8.5.52 0x52 0x00FF JESD_ERR_OUT JESD Error Output 8.5.53 0x53 0x0100 JESD_ILA_CFG1 JESD Configuration Value used for ILA Check 8.5.54 0x54 0x8E60 JESD_ILA_CFG2 JESD Configuration Value used for ILA Check 8.5.55 0x55-0x5B 0x0000 Reserved Reserved 0x5C 0x0001 JESD_SYSR_MODE JESD SYSREF Mode 8.5.56 0x5D-0x5E 0x0000 Reserved Reserved 0x5F 0x0123 JESD_CROSSBAR1 JESD Crossbar Configuration 1 8.5.57 0x60 0x4567 JESD_CROSSBAR2 JESD Crossbar Configuration 2 8.5.58 0x61-0x63 0x0000 Reserved Reserved 0x64 0x0000 JESD_ALM_L0 JESD Alarms for Lane 0 8.5.59 0x65 0x0000 JESD_ ALM_L1 JESD Alarms for Lane 1 8.5.60 0x66 0x0000 JESD_ ALM_L2 JESD Alarms for Lane 2 8.5.61 0x67 0x0000 JESD_ALM_L3 JESD Alarms for Lane 3 8.5.62 0x68 0x0000 JESD_ALM_L4 JESD Alarms for Lane 4 8.5.63 0x69 0x0000 JESD_ALM_L5 JESD Alarms for Lane 5 8.5.64 0x6A 0x0000 JESD_ALM_L6 JESD Alarms for Lane 6 8.5.65 0x6B 0x0000 JESD_ALM_L7 JESD Alarms for Lane 7 8.5.66 0x6C 0x0000 ALM_SYSREF_PAP SYSREF and PAP Alarms 8.5.67 0x6D 0x0000 ALM_CLKDIV1 Clock Divider Alarms 1 8.5.68 0x6E-0x77 0x0000 Reserved Reserved Miscellaneous Configuration Registers (PAGE_SET[1:0] = 00, PAGE_SET[2] = 1) 0x0A 0xFC03 CLK_CONFIG Clock Configuration 8.5.69 |
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