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DAC38RF86 Datasheet(PDF) 97 Page - Texas Instruments

Part # DAC38RF86
Description  DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL
PDF  147 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC38RF86 Datasheet(HTML) 97 Page - Texas Instruments

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97
DAC38RF86, DAC38RF96
DAC38RF87, DAC38RF97
www.ti.com
SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017
Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
8.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
Figure 103. JESD ID 2 Register (JESD_ID2)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
0
1
0
0
0
1
1
1
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 85. JESD ID 2 Register (JESD_ID2)
Bit
Field
Type
Reset
Description
15:11
LID3
R/W
00011
JESD ID for lane 3
10:6
LID4
R/W
00100
JESD ID for lane 4
5:1
LID5
R/W
00101
JESD ID for lane 5
0
Reserved
R/W
0
Reserved
8.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
Figure 104. JESD ID 3 Register (JESD_ID3)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
1
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 86. JESD_ID3 Field Descriptions
Bit
Field
Type
Reset
Description
15:11
LID6
R/W
00110
JESD ID for lane 6
10:6
LID7
R/W
00111
JESD ID for lane 7
5:4
Reserved
R/W
00
Reserved
3:1
SUBCLASSV
R/W
001
Selects the JESD subclass supported. Note: “001” is subclass 1
and “000” is subclass 0 they are the only modes supported; not
used for operation but used for configuration. See field
MIN_LATENCY_ENA in register JESD_MATCH (9.5.46) for use
in subclass0
0
JESDV
R/W
1
Selects the version of JESD support(0=A; 1=B) NOTE: JESD
204B is only supported version.



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