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DAC38RF86 Datasheet(PDF) 36 Page - Texas Instruments

Part # DAC38RF86
Description  DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL
PDF  147 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC38RF86 Datasheet(HTML) 36 Page - Texas Instruments

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36
DAC38RF86, DAC38RF96
DAC38RF87, DAC38RF97
SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017
www.ti.com
Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Table 12. JESD204B Frame Format for LMFSHd = 84111 (continued)
lane RX5
B-i0[7:0]
lane RX6
B-q0[15:8]
lane RX7
B-q0[7:0]
Table 13. JESD204B Frame Format for LMFSHd = 22210
# un bits
4
8
12
16
# en bits
5
10
15
20
Nibble
1
2
3
4
lane RX0
i0
lane RX1
q0
(1)
DAC A, I sample 0
Table 14. JESD204B Frame Format for LMFSHd = 44210
# un bits
4
8
12
16
# en bits
5
10
15
20
Nibble
1
2
3
4
lane RX0
A-i0(1)
lane RX1
A-q0
lane RX2
B-i0
lane RX3
B-q0
Table 15. JESD204B Frame Format for LMFSHd = 12410
# un bits
4
8
12
16
20
24
28
32
# en bits
5
10
15
20
25
30
35
40
Nibble
1
2
3
4
5
6
7
8
lane RX0
i0
q0
(1)
DAC A, I sample 0
Table 16. JESD204B Frame Format for LMFSHd = 24410
# un bits
4
8
12
16
20
24
28
32
# en bits
5
10
15
20
25
30
35
40
Nibble
1
2
3
4
5
6
7
8
lane RX0
A-i0(1)
A-q0
lane RX1
B-i0
B-q0
(1)
DAC A, MultiDUC 1, I sample 0
(2)
DAC A, MultiDUC 2, I sample 0
Table 17. JESD204B Frame Format for LMFSHd = 44210
# un bits
4
8
12
16
# en bits
5
10
15
20
Nibble
1
2
3
4
lane RX0
A1-i0(1)
lane RX1
A1-q0(2)
lane RX2
A2-i0
lane RX3
A2-q0



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