DAC38RF86 datasheet(64/147 Pages) TI2

64 / 147 page

50 :

RLOAD

VOUT1/2

IOUT

CODE

IOUT-

16383

16384

IOUT

CODE

IOUT+

16384

DAC38RF86, DAC38RF96

DAC38RF87, DAC38RF97

SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017

www.ti.com

Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97

Submit Documentation Feedback

(12)

(13)

where CODE is the decimal representation of the 14-bit DAC core data input word. Note the signal path up to the

DAC is 16-bits and the 2 LSBs are truncated for the DAC core data input word.

8.3.29 DAC Transfer Function

The DAC38RFxx has a wide bandwidth integrated balun (nominally 700 MHz to 3.8 GHz passband) to convert

the DAC core differential signal to a single ended signal. The single ended output is expected to drive a 50-Ω

load (see Figure 56). With full-scale current of 40 mA, the theoretical output power delivered to a 50-Ω load is 4

dBm. However the actual power delivered will be less than the theoretical value and Figure 13 shows the output

power across frequency.

Figure 56. Driving a 50-Ω Load

8.4 Device Functional Modes

8.4.1 Clocking Modes

The DAC38RFxx has both a single ended clock input DACCLKSE and a differential clock input DACCLK+/- to

clock the device. The clock input is selected by field SEL_EXTCLK_DIFFSE in register CLK_PLL_CFG (8.5.79).

The DAC38RFxx can be clocked directly with a high frequency input clock at the DAC sample rate (PLL Bypass

Mode), or an optional on-chip low-jitter phase-locked loop (PLL) can be used to generate the high frequency

DAC sample clock internally from a lower frequency reference clock input (PLL Mode).

8.4.2 PLL Bypass Mode Programming

In PLL bypass mode a high quality clock is sourced to the DACCLK inputs. This clock is used to directly clock

the DAC38RFxx DAC cores. This mode gives the device best performance and is recommended for extremely

demanding applications.

The bypass mode is selected by setting the following:

1. Set field PLL_ENA in register CLK_PLL_CFG (8.5.79) to “0” to bypass the PLL circuitry.

2. Set field PLL_SLEEP in register SLEEP_CONFIG (8.5.70) to “1” to put the PLL and VCO into sleep mode.

8.4.3 Internal PLL/VCO

The DAC38RFxx has an internal clock generation circuit consisting of a PLL and two identical VCOs connected

in parallel, as shown in Figure 57.

DAC38RF86 Datasheet(PDF) 64 Page - Texas Instruments

DAC38RF86 Datasheet(HTML) 64 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL