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DAC38RF86 Datasheet(PDF) 4 Page - Texas Instruments

Part # DAC38RF86
Description  DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL
PDF  147 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC38RF86 Datasheet(HTML) 4 Page - Texas Instruments

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DAC38RF86, DAC38RF96
DAC38RF87, DAC38RF97
SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017
www.ti.com
Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97
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Copyright © 2017, Texas Instruments Incorporated
Changes from Original (February 2017) to Revision A
Page
•
Changed the Title From: "Dual- or Single-Channel, Single-Ended, 14-bit, 9-GSPS,.." To: Dual-Channel, Single-
Ended, 14-bit, 6 & 9-GSPS,..." ............................................................................................................................................... 1
•
Changed the Description of SYSREF+ From: "LVPECL SYSREF positive input." To: "LVPECL SYSREF positive
input, self biased." in the Pin Functions table......................................................................................................................... 8
•
Deleted Latency and PLL/VCO parameters from the end of the Electrical Characteristics - DC Specifications table ........ 15
•
Changed the Electrical Characteristics - AC Specifications table, and added "0 dBFS" amplitude of input digital data
in test conditions ................................................................................................................................................................... 16
•
Added the PLL/VCO Electrical Characteristics table............................................................................................................ 19
•
Added JESD204B clock phase register setting to Table 36 ................................................................................................ 55
•
Removed descriptions for CLKJESD_DIV register from Table 36 ...................................................................................... 55
•
Added JESD204B clock phase register setting to Table 37 ................................................................................................ 55
•
Added information about the DAC output total current for various full scale current settings in DAC Fullscale Output
Current ................................................................................................................................................................................. 62
•
Changed Table 125 ........................................................................................................................................................... 125
•
Changed description of SERDES_REFCLK_DIV register field in Table 126 .................................................................... 126
•
Changed Bit 12:11, 6:5 and 4:2 of Table 129 ................................................................................................................... 128



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