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DAC38RF86 Datasheet(PDF) 89 Page - Texas Instruments

Part # DAC38RF86
Description  DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL
PDF  147 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC38RF86 Datasheet(HTML) 89 Page - Texas Instruments

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DAC38RF86, DAC38RF96
DAC38RF87, DAC38RF97
www.ti.com
SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017
Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
8.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
Figure 88. Serdes Clock Control Register (SERDES_CLK)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
1
0
0
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 70. SERDES_CLK Field Descriptions
Bit
Field
Type
Reset
Description
15:12
CLKJESD_DIV
R/W
0x7
This controls the selection of the clk_jesd output
0000 = div4
0001 = div8
0010 = div12
0011 = div16
0100 = div18
0101 = div20
0110 = div24
0111 = div32
1001 = div36
1010 = div48
1011 = div64
1100 = div5.333
1101 = div10.666
1110 = div21p333
11:8
CLKJESD_OUT_DIV
R/W
0x7
This controls the selection of the clk_jesd_out output
0000 = div8
0001 = div16
0010 = div32
0011 = div48
0100 = div64
0101 = div80
0110 = div96
0111 = div128
1000 = div144
1001 = div160
1010 = div192
7:0
Reserved
R/W
0x0
Reserved



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