LPC3240 datasheet(29/80 Pages) NXP

29 / 80 page

LPC3220_30_40_50

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Product data sheet

Rev. 2.1 — 24 June 2014

29 of 80

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

7.5.1.2

Single-Level Cell (SLC) NAND flash controller

The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page

transfers are supported, including a 20-byte DMA read and write FIFO. Hardware support

for ECC (Error Checking and Correction) is included for the main data area. Software can

correct a single bit error.

7.5.2 SD card controller

The SD interface allows access to external SD memory cards. The SD card interface

conforms to the SD Memory Card Specification Version 1.01.

7.5.2.1

Features

• 1-bit and 4-bit data line interface support.

• DMA is supported through the system DMA controller.

• Provides all functions specific to the SD memory card. These include the clock

generation unit, power management control, command and data transfer.

7.5.3 External memory controller

The LPC3220/30/40/50 includes a memory controller that supports data bus SDRAM,

DDR SDRAM, and static memory devices. The memory controller provides an interface

between the system bus and external (off-chip) memory devices.

The controller supports 16-bit and 32-bit wide SDR SDRAM devices of 64 Mbit, 128 Mbit,

128 Mbit, 256 Mbit, and 512 Mbit sizes, as well as 16-bit wide data bus DDR SDRAM

devices of 64 Mbit, 128 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit sizes. Two dynamic

memory chip selects are supplied, supporting two groups of SDRAM:

• DYCS0 in the address range 0x8000 0000 to 0x9FFF FFFF

• DYCS1 in the address range 0xA000 0000 to 0xBFFF FFFF

The memory controller also supports 8-bit, 16-bit, and 32-bit wide asynchronous static

memory devices, including RAM, ROM, and flash, with or without asynchronous page

mode. Four static memory chip selects are supplied for SRAM devices:

• CS0 in the address range 0xE000 0000 to 0xE0FF FFFF

• CS1 in the address range 0xE100 0000 to 0xE1FF FFFF

• CS2 in the address range 0xE200 0000 to 0xE2FF FFFF

• CS3 in the address range 0xE300 0000 to 0xE3FF FFFF

The SDRAM controller uses three data ports to allow simultaneous requests from multiple

on-chip AHB bus masters and has the following features.

• Dynamic memory interface supports SDRAM, DDR-SDRAM, and low-power variants.

• Read and write buffers to reduce latency and improve performance.

• Static memory features include

– asynchronous page mode read

– programmable wait states

– bus turnaround cycles

– output enable and write enable delays

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